InstSimplify: Simplify trivial and/or of icmps
Some ICmpInsts when anded/ored with another ICmpInst trivially reduces
to true or false depending on whether or not all integers or no integers
satisfy the intersected/unioned range.
This sort of trivial looking code can come about when InstCombine
performs a range reduction-type operation on sdiv and the like.
This fixes PR20916.
llvm-svn: 217750
diff --git a/llvm/test/Transforms/InstSimplify/AndOrXor.ll b/llvm/test/Transforms/InstSimplify/AndOrXor.ll
index 0277d39..8ed06e8 100644
--- a/llvm/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/llvm/test/Transforms/InstSimplify/AndOrXor.ll
@@ -28,3 +28,123 @@
ret i32 %sub
; CHECK: ret i32 %x
}
+
+define i1 @and_of_icmps0(i32 %b) {
+; CHECK-LABEL: @and_of_icmps0(
+ %1 = add i32 %b, 2
+ %2 = icmp ult i32 %1, 4
+ %cmp3 = icmp sgt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @and_of_icmps1(i32 %b) {
+; CHECK-LABEL: @and_of_icmps1(
+ %1 = add nsw i32 %b, 2
+ %2 = icmp slt i32 %1, 4
+ %cmp3 = icmp sgt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @and_of_icmps2(i32 %b) {
+; CHECK-LABEL: @and_of_icmps2(
+ %1 = add i32 %b, 2
+ %2 = icmp ule i32 %1, 3
+ %cmp3 = icmp sgt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @and_of_icmps3(i32 %b) {
+; CHECK-LABEL: @and_of_icmps3(
+ %1 = add nsw i32 %b, 2
+ %2 = icmp sle i32 %1, 3
+ %cmp3 = icmp sgt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @and_of_icmps4(i32 %b) {
+; CHECK-LABEL: @and_of_icmps4(
+ %1 = add nuw i32 %b, 2
+ %2 = icmp ult i32 %1, 4
+ %cmp3 = icmp ugt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @and_of_icmps5(i32 %b) {
+; CHECK-LABEL: @and_of_icmps5(
+ %1 = add nuw i32 %b, 2
+ %2 = icmp ule i32 %1, 3
+ %cmp3 = icmp ugt i32 %b, 2
+ %cmp = and i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 false
+}
+
+define i1 @or_of_icmps0(i32 %b) {
+; CHECK-LABEL: @or_of_icmps0(
+ %1 = add i32 %b, 2
+ %2 = icmp uge i32 %1, 4
+ %cmp3 = icmp sle i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
+
+define i1 @or_of_icmps1(i32 %b) {
+; CHECK-LABEL: @or_of_icmps1(
+ %1 = add nsw i32 %b, 2
+ %2 = icmp sge i32 %1, 4
+ %cmp3 = icmp sle i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
+
+define i1 @or_of_icmps2(i32 %b) {
+; CHECK-LABEL: @or_of_icmps2(
+ %1 = add i32 %b, 2
+ %2 = icmp ugt i32 %1, 3
+ %cmp3 = icmp sle i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
+
+define i1 @or_of_icmps3(i32 %b) {
+; CHECK-LABEL: @or_of_icmps3(
+ %1 = add nsw i32 %b, 2
+ %2 = icmp sgt i32 %1, 3
+ %cmp3 = icmp sle i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
+
+define i1 @or_of_icmps4(i32 %b) {
+; CHECK-LABEL: @or_of_icmps4(
+ %1 = add nuw i32 %b, 2
+ %2 = icmp uge i32 %1, 4
+ %cmp3 = icmp ule i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}
+
+define i1 @or_of_icmps5(i32 %b) {
+; CHECK-LABEL: @or_of_icmps5(
+ %1 = add nuw i32 %b, 2
+ %2 = icmp ugt i32 %1, 3
+ %cmp3 = icmp ule i32 %b, 2
+ %cmp = or i1 %2, %cmp3
+ ret i1 %cmp
+; CHECK: ret i1 true
+}