Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index bc4f3e7..6d23657 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -19,10 +19,10 @@
// PowerPC Subtarget features.
//
-def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true",
+def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
-def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true",
- "Enable 64-bit registers [beta]">;
+def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
+ "Enable 64-bit registers usage for ppc32 [beta]">;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
"Enable Altivec instructions">;
def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index a0142b1..ff42fa0 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -146,7 +146,7 @@
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
+ if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
// They also have instructions for converting between i64 and fp.
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
@@ -163,7 +163,7 @@
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
}
- if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
+ if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
// 64 bit PowerPC implementations can support i64 types directly
addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
@@ -2227,7 +2227,7 @@
switch (N->getOpcode()) {
default: break;
case ISD::SINT_TO_FP:
- if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
+ if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
// Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
// We allow the src/dst to be either f32/f64, but the intermediate
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 607771b..b228ba7 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -73,8 +73,8 @@
: StackAlignment(16)
, InstrItins()
, IsGigaProcessor(false)
- , Is64Bit(false)
- , Has64BitRegs(false)
+ , Has64BitSupport(false)
+ , Use64BitRegs(false)
, HasAltivec(false)
, HasFSQRT(false)
, HasSTFIWX(false)
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index c98291e..e898a04 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -33,8 +33,8 @@
/// Used by the ISel to turn in optimizations for POWER4-derived architectures
bool IsGigaProcessor;
- bool Is64Bit;
- bool Has64BitRegs;
+ bool Has64BitSupport;
+ bool Use64BitRegs;
bool HasAltivec;
bool HasFSQRT;
bool HasSTFIWX;
@@ -66,12 +66,12 @@
bool hasFSQRT() const { return HasFSQRT; }
bool hasSTFIWX() const { return HasSTFIWX; }
- bool has64BitRegs() const { return Has64BitRegs; }
+ bool use64BitRegs() const { return Use64BitRegs; }
bool hasAltivec() const { return HasAltivec; }
bool isAIX() const { return IsAIX; }
bool isDarwin() const { return IsDarwin; }
- bool is64Bit() const { return Is64Bit; }
+ bool has64BitSupport() const { return Has64BitSupport; }
bool isGigaProcessor() const { return IsGigaProcessor; }
};
} // End llvm namespace