Add definitions for "armv6m", which indicates a Cortex-M0 processor.
It uses the T16 and a few T32 instructions from the ARMv7-A ISA.
<rdar://problem/15099306>
llvm-svn: 191587
diff --git a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
index 099b72a..61c3c64 100644
--- a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
+++ b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
@@ -641,9 +641,15 @@
}
// Cortex-M3 devices (e.g. armv7m) can only execute thumb (T2) instructions,
- // so hardcode the primary disassembler to thumb mode.
+ // so hardcode the primary disassembler to thumb mode. Same for Cortex-M4 (armv7em).
+ //
+ // Handle the Cortex-M0 (armv6m) the same; the ISA is a subset of the T and T32
+ // instructions defined in ARMv7-A.
+
if (arch.GetTriple().getArch() == llvm::Triple::arm
- && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em))
+ && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m
+ || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em
+ || arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m))
{
triple = thumb_arch.GetTriple().getTriple().c_str();
}