| commit | a3dc9490004ce1601fb1bc67cf218b86a6fdf652 | [log] [tgz] |
|---|---|---|
| author | WangTianQing <tianqing.wang@intel.com> | Thu Apr 09 13:15:42 2020 +0800 |
| committer | Xiang1 Zhang <xiang1.zhang@intel.com> | Thu Apr 09 13:17:29 2020 +0800 |
| tree | 971748b694dc075f1540c047a8d1c099def02c51 | |
| parent | 2bcf5793e14577ed3c9f15a77a35179ae544fff4 [diff] [blame] |
[X86] Add TSXLDTRK instructions. Summary: For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Reviewers: craig.topper, RKSimon, LuoYuanke Reviewed By: craig.topper Subscribers: mgorny, hiraditya, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D77205
diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 6b8f7ca..f236456 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp
@@ -1478,6 +1478,7 @@ Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1); + Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1); // There are two CPUID leafs which information associated with the pconfig // instruction: // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th