Fix some Clang-tidy and Include What You Use warnings; other minor fixes (NFC).
This preparation to remove SetVector.h dependency on SmallSet.h.
llvm-svn: 288256
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 70cea1f..5fab4a9 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -13,33 +13,53 @@
//===----------------------------------------------------------------------===//
#include "AsmWriterInst.h"
+#include "CodeGenInstruction.h"
+#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "SequenceToOffsetTable.h"
#include "Types.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <algorithm>
#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <deque>
+#include <iterator>
#include <map>
+#include <set>
+#include <string>
+#include <tuple>
#include <utility>
#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "asm-writer-emitter"
namespace {
+
class AsmWriterEmitter {
RecordKeeper &Records;
CodeGenTarget Target;
ArrayRef<const CodeGenInstruction *> NumberedInstructions;
std::vector<AsmWriterInst> Instructions;
+
public:
AsmWriterEmitter(RecordKeeper &R);
@@ -55,10 +75,11 @@
std::vector<unsigned> &InstOpsUsed,
bool PassSubtarget) const;
};
+
} // end anonymous namespace
static void PrintCases(std::vector<std::pair<std::string,
- AsmWriterOperand> > &OpsToPrint, raw_ostream &O,
+ AsmWriterOperand>> &OpsToPrint, raw_ostream &O,
bool PassSubtarget) {
O << " case " << OpsToPrint.back().first << ":";
AsmWriterOperand TheOp = OpsToPrint.back().second;
@@ -77,7 +98,6 @@
O << "\n break;\n";
}
-
/// EmitInstructions - Emit the last instruction in the vector and any other
/// instructions that are suitably similar to it.
static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
@@ -116,7 +136,7 @@
// emit a switch for just this operand now.
O << " switch (MI->getOpcode()) {\n";
O << " default: llvm_unreachable(\"Unexpected opcode.\");\n";
- std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
+ std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint;
OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
FirstInst.CGI->TheDef->getName(),
FirstInst.Operands[i]));
@@ -141,7 +161,6 @@
std::vector<std::vector<unsigned>> &InstIdxs,
std::vector<unsigned> &InstOpsUsed,
bool PassSubtarget) const {
-
// This vector parallels UniqueOperandCommands, keeping track of which
// instructions each case are used for. It is a comma separated string of
// enums.
@@ -158,7 +177,7 @@
// Check to see if we already have 'Command' in UniqueOperandCommands.
// If not, add it.
- auto I = find(UniqueOperandCommands, Command);
+ auto I = llvm::find(UniqueOperandCommands, Command);
if (I != UniqueOperandCommands.end()) {
size_t idx = I - UniqueOperandCommands.begin();
InstrsForCase[idx] += ", ";
@@ -225,7 +244,6 @@
}
}
-
static void UnescapeString(std::string &Str) {
for (unsigned i = 0; i != Str.size(); ++i) {
if (Str[i] == '\\' && i != Str.size()-1) {
@@ -317,7 +335,7 @@
std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
- while (1) {
+ while (true) {
std::vector<std::string> UniqueOperandCommands;
std::vector<std::vector<unsigned>> InstIdxs;
std::vector<unsigned> NumInstOpsHandled;
@@ -451,7 +469,7 @@
}
// Okay, delete instructions with no operand info left.
- auto I = remove_if(Instructions,
+ auto I = llvm::remove_if(Instructions,
[](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
Instructions.erase(I, Instructions.end());
@@ -584,6 +602,7 @@
}
namespace {
+
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
// they both have the same conditionals. In which case, we cannot print out the
// alias for that pattern.
@@ -593,6 +612,7 @@
std::string Result;
std::string AsmString;
+
public:
IAPrinter(std::string R, std::string AS)
: Result(std::move(R)), AsmString(std::move(AS)) {}
@@ -714,6 +734,7 @@
}
namespace {
+
struct AliasPriorityComparator {
typedef std::pair<CodeGenInstAlias, int> ValueType;
bool operator()(const ValueType &LHS, const ValueType &RHS) {
@@ -727,8 +748,8 @@
return LHS.second > RHS.second;
}
};
-}
+} // end anonymous namespace
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
@@ -803,14 +824,14 @@
NumMIOps += Operand.getMINumOperands();
std::string Cond;
- Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
+ Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
IAP.addCond(Cond);
bool CantHandle = false;
unsigned MIOpNum = 0;
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
- std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
+ std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";
const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
@@ -828,7 +849,7 @@
std::string PrintMethod = Rec->getValueAsString("PrintMethod");
if (PrintMethod != "" && PrintMethod != "printOperand") {
PrintMethodIdx =
- find(PrintMethods, PrintMethod) - PrintMethods.begin();
+ llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin();
if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
PrintMethods.push_back(PrintMethod);
}
@@ -849,7 +870,7 @@
".contains(" + Op + ".getReg())";
} else {
Cond = Op + ".getReg() == MI->getOperand(" +
- llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
+ utostr(IAP.getOpIndex(ROName)) + ").getReg()";
}
} else {
// Assume all printable operands are desired for now. This can be
@@ -867,7 +888,7 @@
break; // No conditions on this operand at all
}
Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
- Op + ", STI, " + llvm::utostr(Entry) + ")";
+ Op + ", STI, " + utostr(Entry) + ")";
}
// for all subcases of ResultOperand::K_Record:
IAP.addCond(Cond);
@@ -878,8 +899,7 @@
// MCInst will. An MCExpr could be present, for example.
IAP.addCond(Op + ".isImm()");
- Cond = Op + ".getImm() == " +
- llvm::itostr(CGA.ResultOperands[i].getImm());
+ Cond = Op + ".getImm() == " + itostr(CGA.ResultOperands[i].getImm());
IAP.addCond(Cond);
break;
}
@@ -1100,7 +1120,6 @@
EmitPrintAliasInstruction(O);
}
-
namespace llvm {
void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) {
@@ -1108,4 +1127,4 @@
AsmWriterEmitter(RK).run(OS);
}
-} // End llvm namespace
+} // end namespace llvm
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 9bcdebd..fc2e5aa 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -13,26 +13,35 @@
//
//===----------------------------------------------------------------------===//
+#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "SubtargetFeatureInfo.h"
-#include "Types.h"
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
+#include <cassert>
+#include <cstdint>
#include <map>
+#include <set>
#include <string>
+#include <utility>
#include <vector>
+
using namespace llvm;
namespace {
class CodeEmitterGen {
RecordKeeper &Records;
+
public:
CodeEmitterGen(RecordKeeper &R) : Records(R) {}
void run(raw_ostream &o);
+
private:
int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
std::string getInstructionCase(Record *R, CodeGenTarget &Target);
@@ -175,7 +184,6 @@
}
}
-
std::string CodeEmitterGen::getInstructionCase(Record *R,
CodeGenTarget &Target) {
std::string Case;
@@ -261,7 +269,7 @@
o << " UINT64_C(0)\n };\n";
// Map to accumulate all the cases.
- std::map<std::string, std::vector<std::string> > CaseMap;
+ std::map<std::string, std::vector<std::string>> CaseMap;
// Construct all cases statement for each opcode
for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
@@ -285,7 +293,7 @@
<< " switch (opcode) {\n";
// Emit each case statement
- std::map<std::string, std::vector<std::string> >::iterator IE, EE;
+ std::map<std::string, std::vector<std::string>>::iterator IE, EE;
for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
const std::string &Case = IE->first;
std::vector<std::string> &InstList = IE->second;
@@ -374,7 +382,7 @@
o << "#endif\n";
}
-} // End anonymous namespace
+} // end anonymous namespace
namespace llvm {
@@ -383,4 +391,4 @@
CodeEmitterGen(RK).run(OS);
}
-} // End llvm namespace
+} // end namespace llvm
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 8eeed81..9fc1392 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -14,13 +14,33 @@
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntEqClasses.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseBitVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
+#include "llvm/TableGen/Record.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <map>
+#include <set>
+#include <string>
+#include <tuple>
+#include <utility>
+#include <vector>
using namespace llvm;
@@ -151,6 +171,7 @@
}
namespace {
+
// Iterate over all register units in a set of registers.
class RegUnitIterator {
CodeGenRegister::Vec::const_iterator RegI, RegE;
@@ -158,7 +179,7 @@
public:
RegUnitIterator(const CodeGenRegister::Vec &Regs):
- RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
+ RegI(Regs.begin()), RegE(Regs.end()) {
if (RegI != RegE) {
UnitI = (*RegI)->getRegUnits().begin();
@@ -190,7 +211,8 @@
}
}
};
-} // namespace
+
+} // end anonymous namespace
// Return true of this unit appears in RegUnits.
static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
@@ -538,6 +560,7 @@
// sub-registers. We provide a SetTheory expander class that returns the new
// registers.
namespace {
+
struct TupleExpander : SetTheory::Expander {
void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
@@ -639,7 +662,8 @@
}
}
};
-}
+
+} // end anonymous namespace
//===----------------------------------------------------------------------===//
// CodeGenRegisterClass
@@ -767,13 +791,15 @@
}
namespace llvm {
+
raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
for (const auto R : *K.Members)
OS << ", " << R->getName();
return OS << " }";
}
-}
+
+} // end namespace llvm
// This is a simple lexicographical order that can be used to search for sets.
// It is not the same as the topological order provided by TopoOrderRC.
@@ -813,7 +839,7 @@
auto *A = &PA;
auto *B = &PB;
if (A == B)
- return 0;
+ return false;
// Order by ascending spill size.
if (A->SpillSize < B->SpillSize)
@@ -1289,6 +1315,7 @@
}
namespace {
+
// UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
// the transitive closure of the union of overlapping register
// classes. Together, the UberRegSets form a partition of the registers. If we
@@ -1307,12 +1334,13 @@
// their weight increased.
struct UberRegSet {
CodeGenRegister::Vec Regs;
- unsigned Weight;
+ unsigned Weight = 0;
CodeGenRegister::RegUnitList SingularDeterminants;
- UberRegSet(): Weight(0) {}
+ UberRegSet() = default;
};
-} // namespace
+
+} // end anonymous namespace
// Partition registers into UberRegSets, where each set is the transitive
// closure of the union of overlapping register classes.
@@ -1321,7 +1349,6 @@
static void computeUberSets(std::vector<UberRegSet> &UberSets,
std::vector<UberRegSet*> &RegSets,
CodeGenRegBank &RegBank) {
-
const auto &Registers = RegBank.getRegisters();
// The Register EnumValue is one greater than its index into Registers.
@@ -1789,7 +1816,7 @@
CodeGenRegister *SubReg = S->second;
// Ignore non-leaf subregisters, their lane masks are fully covered by
// the leaf subregisters anyway.
- if (SubReg->getSubRegs().size() != 0)
+ if (!SubReg->getSubRegs().empty())
continue;
CodeGenSubRegIndex *SubRegIndex = S->first;
const CodeGenRegister *SubRegister = S->second;
@@ -2008,7 +2035,6 @@
}
}
-
//
// Infer missing register classes.
//
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index b8d47aa..827eef8 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -18,20 +18,28 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
-#include <cstdlib>
+#include <cassert>
+#include <cstdint>
#include <deque>
#include <list>
#include <map>
#include <string>
+#include <utility>
#include <vector>
namespace llvm {
+
class CodeGenRegBank;
template <typename T, typename Vector, typename Set> class SetVector;
@@ -41,6 +49,7 @@
struct MaskRolPair {
unsigned Mask;
uint8_t RotateLeft;
+
bool operator==(const MaskRolPair Other) const {
return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
}
@@ -266,7 +275,7 @@
class CodeGenRegisterClass {
CodeGenRegister::Vec Members;
// Allocation orders. Order[0] always contains all registers in Members.
- std::vector<SmallVector<Record*, 16> > Orders;
+ std::vector<SmallVector<Record*, 16>> Orders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
BitVector SubClasses;
// List of super-classes, topologocally ordered to have the larger classes
@@ -463,10 +472,10 @@
std::string Name;
std::vector<unsigned> Units;
- unsigned Weight; // Cache the sum of all unit weights.
- unsigned Order; // Cache the sort key.
+ unsigned Weight = 0; // Cache the sum of all unit weights.
+ unsigned Order = 0; // Cache the sort key.
- RegUnitSet() : Weight(0), Order(0) {}
+ RegUnitSet() = default;
};
// Base vector for identifying TopoSigs. The contents uniquely identify a
@@ -515,7 +524,7 @@
// NOTE: This could grow beyond the number of register classes when we map
// register units to lists of unit sets. If the list of unit sets does not
// already exist for a register class, we create a new entry in this vector.
- std::vector<std::vector<unsigned> > RegClassUnitSets;
+ std::vector<std::vector<unsigned>> RegClassUnitSets;
// Give each register unit set an order based on sorting criteria.
std::vector<unsigned> RegUnitSetOrder;
@@ -532,6 +541,7 @@
void computeInferredRegisterClasses();
void inferCommonSubClass(CodeGenRegisterClass *RC);
void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
+
void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
inferMatchingSuperRegClass(RC, RegClasses.begin());
}
@@ -590,6 +600,7 @@
}
const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
+
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}
@@ -674,6 +685,7 @@
unsigned getRegSetIDAt(unsigned Order) const {
return RegUnitSetOrder[Order];
}
+
const RegUnitSet &getRegSetAt(unsigned Order) const {
return RegUnitSets[RegUnitSetOrder[Order]];
}
@@ -723,6 +735,7 @@
// another sub-register with the same or larger lane mask.
unsigned CoveringLanes;
};
-}
-#endif
+} // end namespace llvm
+
+#endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 4cc600d..cae1cf4 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -12,12 +12,21 @@
//
//===----------------------------------------------------------------------===//
+#include "CodeGenInstruction.h"
#include "CodeGenSchedule.h"
#include "CodeGenTarget.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Regex.h"
#include "llvm/TableGen/Error.h"
+#include <algorithm>
+#include <iterator>
+#include <utility>
using namespace llvm;
@@ -31,6 +40,7 @@
#endif
namespace {
+
// (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp.
struct InstrsOp : public SetTheory::Operator {
void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts,
@@ -76,6 +86,7 @@
}
}
};
+
} // end anonymous namespace
/// CodeGenModels ctor interprets machine model records and populates maps.
@@ -364,6 +375,7 @@
}
namespace llvm {
+
void splitSchedReadWrites(const RecVec &RWDefs,
RecVec &WriteDefs, RecVec &ReadDefs) {
for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
@@ -375,7 +387,8 @@
}
}
}
-} // namespace llvm
+
+} // end namespace llvm
// Split the SchedReadWrites defs and call findRWs for each list.
void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
@@ -676,7 +689,7 @@
// intersects with an existing class via a previous InstRWDef. Instrs that do
// not intersect with an existing class refer back to their former class as
// determined from ItinDef or SchedRW.
- SmallVector<std::pair<unsigned, SmallVector<Record *, 8> >, 4> ClassInstrs;
+ SmallVector<std::pair<unsigned, SmallVector<Record *, 8>>, 4> ClassInstrs;
// Sort Instrs into sets.
const RecVec *InstDefs = Sets.expand(InstRWDef);
if (InstDefs->empty())
@@ -915,6 +928,7 @@
}
namespace {
+
// Helper for substituteVariantOperand.
struct TransVariant {
Record *VarOrSeqDef; // Variant or sequence.
@@ -971,7 +985,8 @@
std::vector<TransVariant> &IntersectingVariants);
void pushVariant(const TransVariant &VInfo, bool IsRead);
};
-} // anonymous
+
+} // end anonymous namespace
// Return true if this predicate is mutually exclusive with a PredTerm. This
// degenerates into checking if the predicate is mutually exclusive with any
@@ -984,7 +999,6 @@
// conditions implicitly negate any prior condition.
bool PredTransitions::mutuallyExclusive(Record *PredDef,
ArrayRef<PredCheck> Term) {
-
for (ArrayRef<PredCheck>::iterator I = Term.begin(), E = Term.end();
I != E; ++I) {
if (I->Predicate == PredDef)
@@ -1031,7 +1045,7 @@
for (ArrayRef<PredTransition>::iterator
PTI = Transitions.begin(), PTE = Transitions.end();
PTI != PTE; ++PTI) {
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = PTI->WriteSequences.begin(), WSE = PTI->WriteSequences.end();
WSI != WSE; ++WSI) {
for (SmallVectorImpl<unsigned>::const_iterator
@@ -1040,7 +1054,7 @@
return true;
}
}
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end();
RSI != RSE; ++RSI) {
for (SmallVectorImpl<unsigned>::const_iterator
@@ -1147,7 +1161,6 @@
// specified by VInfo.
void PredTransitions::
pushVariant(const TransVariant &VInfo, bool IsRead) {
-
PredTransition &Trans = TransVec[VInfo.TransVecIdx];
// If this operand transition is reached through a processor-specific alias,
@@ -1170,7 +1183,7 @@
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead);
- SmallVectorImpl<SmallVector<unsigned,4> > &RWSequences = IsRead
+ SmallVectorImpl<SmallVector<unsigned,4>> &RWSequences = IsRead
? Trans.ReadSequences : Trans.WriteSequences;
if (SchedRW.IsVariadic) {
unsigned OperIdx = RWSequences.size()-1;
@@ -1266,7 +1279,7 @@
TransVec.back().ProcIndices = Trans.ProcIndices;
// Visit each original write sequence.
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end();
WSI != WSE; ++WSI) {
// Push a new (empty) write sequence onto all partial Transitions.
@@ -1277,7 +1290,7 @@
substituteVariantOperand(*WSI, /*IsRead=*/false, StartIdx);
}
// Visit each original read sequence.
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end();
RSI != RSE; ++RSI) {
// Push a new (empty) read sequence onto all partial Transitions.
@@ -1298,7 +1311,7 @@
for (ArrayRef<PredTransition>::iterator
I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) {
IdxVec OperWritesVariant;
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = I->WriteSequences.begin(), WSE = I->WriteSequences.end();
WSI != WSE; ++WSI) {
// Create a new write representing the expanded sequence.
@@ -1306,7 +1319,7 @@
SchedModels.findOrInsertRW(*WSI, /*IsRead=*/false));
}
IdxVec OperReadsVariant;
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end();
RSI != RSE; ++RSI) {
// Create a new read representing the expanded sequence.
@@ -1658,7 +1671,6 @@
void CodeGenSchedModels::collectRWResources(ArrayRef<unsigned> Writes,
ArrayRef<unsigned> Reads,
ArrayRef<unsigned> ProcIndices) {
-
for (unsigned Idx : Writes)
collectRWResources(Idx, /*IsRead=*/false, ProcIndices);
@@ -1666,7 +1678,6 @@
collectRWResources(Idx, /*IsRead=*/true, ProcIndices);
}
-
// Find the processor's resource units for this kind of resource.
Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
const CodeGenProcModel &PM) const {
@@ -1714,7 +1725,7 @@
// Iteratively add a resource and its super resources.
void CodeGenSchedModels::addProcResource(Record *ProcResKind,
CodeGenProcModel &PM) {
- for (;;) {
+ while (true) {
Record *ProcResUnits = findProcResUnits(ProcResKind, PM);
// See if this ProcResource is already associated with this processor.
@@ -1835,7 +1846,7 @@
<< ":" << PCI->Predicate->getName();
}
dbgs() << "},\n => {";
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
WSI = TI->WriteSequences.begin(), WSE = TI->WriteSequences.end();
WSI != WSE; ++WSI) {
dbgs() << "(";
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index e31caaf..f879a5b 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -19,14 +19,18 @@
#include "CodeGenTarget.h"
#include "llvm/ADT/DenseSet.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <cstdint>
#include <map>
+#include <set>
#include <string>
-#include <queue>
+#include <vector>
using namespace llvm;
@@ -58,6 +62,7 @@
#define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
namespace {
+
DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
}
@@ -67,12 +72,13 @@
/// DFAPacketizerEmitter.cpp.
DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
DFAInput InsnInput = 0;
- assert ((InsnClass.size() <= DFA_MAX_RESTERMS) &&
- "Exceeded maximum number of DFA terms");
+ assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
+ "Exceeded maximum number of DFA terms");
for (auto U : InsnClass)
InsnInput = addDFAFuncUnits(InsnInput, U);
return InsnInput;
}
+
} // end anonymous namespace
// --------------------------------------------------------------------
@@ -98,6 +104,7 @@
// for resource tracking.
//
namespace {
+
class DFAPacketizerEmitter {
private:
std::string TargetName;
@@ -150,10 +157,8 @@
void run(raw_ostream &OS);
};
-} // end anonymous namespace
//
-//
// State represents the usage of machine resources if the packet contains
// a set of instruction classes.
//
@@ -174,7 +179,6 @@
// A State instance also contains a collection of transitions from that state:
// a map from inputs to new states.
//
-namespace {
class State {
public:
static int currentStateNum;
@@ -204,6 +208,7 @@
//
bool canMaybeAddInsnClass(std::vector<unsigned> &InsnClass,
std::map<unsigned, unsigned> &ComboBitToBitsMap) const;
+
//
// AddInsnClass - Return all combinations of resource reservation
// which are possible from this state (PossibleStates).
@@ -214,6 +219,7 @@
void AddInsnClass(std::vector<unsigned> &InsnClass,
std::map<unsigned, unsigned> &ComboBitToBitsMap,
std::set<unsigned> &PossibleStates) const;
+
//
// AddInsnClassStages - Return all combinations of resource reservation
// resulting from the cross product of all stages for this InsnClass
@@ -225,31 +231,31 @@
unsigned prevState, unsigned origState,
DenseSet<unsigned> &VisitedResourceStates,
std::set<unsigned> &PossibleStates) const;
+
//
// addTransition - Add a transition from this state given the input InsnClass
//
void addTransition(std::vector<unsigned> InsnClass, const State *To) const;
+
//
// hasTransition - Returns true if there is a transition from this state
// given the input InsnClass
//
bool hasTransition(std::vector<unsigned> InsnClass) const;
};
-} // end anonymous namespace
//
// class DFA: deterministic finite automaton for processor resource tracking.
//
-namespace {
class DFA {
public:
- DFA();
+ DFA() = default;
// Set of states. Need to keep this sorted to emit the transition table.
typedef std::set<State> StateSet;
StateSet states;
- State *currentState;
+ State *currentState = nullptr;
//
// Modify the DFA.
@@ -263,6 +269,7 @@
int numInsnClasses = 0,
int maxResources = 0, int numCombos = 0, int maxStages = 0);
};
+
} // end anonymous namespace
#ifndef NDEBUG
@@ -314,8 +321,6 @@
State::State() :
stateNum(currentStateNum++), isInitial(false) {}
-DFA::DFA(): currentState(nullptr) {}
-
//
// addTransition - Add a transition from this state given the input InsnClass
//
@@ -370,7 +375,6 @@
unsigned prevState, unsigned origState,
DenseSet<unsigned> &VisitedResourceStates,
std::set<unsigned> &PossibleStates) const {
-
assert((chkstage < numstages) && "AddInsnClassStages: stage out of range");
unsigned thisStage = InsnClass[chkstage];
@@ -469,7 +473,6 @@
std::map<unsigned, unsigned> &ComboBitToBitsMap) const {
for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
SI != stateInfo.end(); ++SI) {
-
// Check to see if all required resources are available.
bool available = true;
@@ -514,8 +517,7 @@
int State::currentStateNum = 0;
DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
- TargetName(CodeGenTarget(R).getName()),
- allInsnClasses(), Records(R) {}
+ TargetName(CodeGenTarget(R).getName()), Records(R) {}
//
// writeTableAndAPI - Print out a table representing the DFA and the
@@ -531,7 +533,6 @@
void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName,
int numInsnClasses,
int maxResources, int numCombos, int maxStages) {
-
unsigned numStates = states.size();
DEBUG(dbgs() << "-----------------------------------------------------------------------------\n");
@@ -783,7 +784,7 @@
DEBUG(dbgs() << " (bits: 0x" << utohexstr(UnitBitValue) << ")\n");
}
- if (UnitBits.size() > 0)
+ if (!UnitBits.empty())
allInsnClasses.push_back(UnitBits);
DEBUG({
@@ -831,7 +832,6 @@
// Run the worklist algorithm to generate the DFA.
//
void DFAPacketizerEmitter::run(raw_ostream &OS) {
-
// Collect processor iteraries.
std::vector<Record*> ProcItinList =
Records.getAllDerivedDefinitions("ProcessorItineraries");
@@ -890,7 +890,6 @@
Initial->isInitial = true;
Initial->stateInfo.insert(0x0);
SmallVector<const State*, 32> WorkList;
-// std::queue<State*> WorkList;
std::map<std::set<unsigned>, const State*> Visited;
WorkList.push_back(Initial);
@@ -937,7 +936,7 @@
current->canMaybeAddInsnClass(InsnClass, ComboBitToBitsMap)) {
const State *NewState = nullptr;
current->AddInsnClass(InsnClass, ComboBitToBitsMap, NewStateResources);
- if (NewStateResources.size() == 0) {
+ if (NewStateResources.empty()) {
DEBUG(dbgs() << " Skipped - no new states generated\n");
continue;
}
@@ -989,4 +988,4 @@
DFAPacketizerEmitter(RK).run(OS);
}
-} // end namespaec llvm
+} // end namespace llvm
diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index f2d54e6..a20b469 100644
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -12,22 +12,32 @@
//
//===----------------------------------------------------------------------===//
+#include "CodeGenInstruction.h"
#include "CodeGenTarget.h"
#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/CachedHashString.h"
#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
-#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
+#include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
#include <map>
+#include <memory>
+#include <set>
#include <string>
#include <utility>
#include <vector>
@@ -37,6 +47,7 @@
#define DEBUG_TYPE "decoder-emitter"
namespace {
+
struct EncodingField {
unsigned Base, Width, Offset;
EncodingField(unsigned B, unsigned W, unsigned O)
@@ -76,13 +87,10 @@
DecoderSet Decoders;
};
-} // End anonymous namespace
-
-namespace {
class FixedLenDecoderEmitter {
ArrayRef<const CodeGenInstruction *> NumberedInstructions;
-public:
+public:
// Defaults preserved here for documentation, even though they aren't
// strictly necessary given the way that this is currently being called.
FixedLenDecoderEmitter(RecordKeeper &R, std::string PredicateNamespace,
@@ -112,13 +120,15 @@
private:
CodeGenTarget Target;
+
public:
std::string PredicateNamespace;
std::string GuardPrefix, GuardPostfix;
std::string ReturnOK, ReturnFail;
std::string Locals;
};
-} // End anonymous namespace
+
+} // end anonymous namespace
// The set (BIT_TRUE, BIT_FALSE, BIT_UNSET) represents a ternary logic system
// for a bit value.
@@ -135,12 +145,15 @@
static bool ValueSet(bit_value_t V) {
return (V == BIT_TRUE || V == BIT_FALSE);
}
+
static bool ValueNotSet(bit_value_t V) {
return (V == BIT_UNSET);
}
+
static int Value(bit_value_t V) {
return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1);
}
+
static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) {
if (BitInit *bit = dyn_cast<BitInit>(bits.getBit(index)))
return bit->getValue() ? BIT_TRUE : BIT_FALSE;
@@ -148,6 +161,7 @@
// The bit is uninitialized.
return BIT_UNSET;
}
+
// Prints the bit value for each position.
static void dumpBits(raw_ostream &o, const BitsInit &bits) {
for (unsigned index = bits.getNumBits(); index > 0; --index) {
@@ -172,14 +186,13 @@
return *bits;
}
-// Forward declaration.
-namespace {
-class FilterChooser;
-} // End anonymous namespace
-
// Representation of the instruction to work on.
typedef std::vector<bit_value_t> insn_t;
+namespace {
+
+class FilterChooser;
+
/// Filter - Filter works with FilterChooser to produce the decoding tree for
/// the ISA.
///
@@ -216,7 +229,6 @@
/// decoder could try to decode the even/odd register numbering and assign to
/// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a"
/// version and return the Opcode since the two have the same Asm format string.
-namespace {
class Filter {
protected:
const FilterChooser *Owner;// points to the FilterChooser who owns this filter
@@ -225,7 +237,7 @@
bool Mixed; // a mixed region contains both set and unset bits
// Map of well-known segment value to the set of uid's with that value.
- std::map<uint64_t, std::vector<unsigned> > FilteredInstructions;
+ std::map<uint64_t, std::vector<unsigned>> FilteredInstructions;
// Set of uid's with non-constant segment values.
std::vector<unsigned> VariableInstructions;
@@ -240,11 +252,18 @@
unsigned LastOpcFiltered;
public:
+ Filter(Filter &&f);
+ Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed);
+
+ ~Filter() = default;
+
unsigned getNumFiltered() const { return NumFiltered; }
+
unsigned getSingletonOpc() const {
assert(NumFiltered == 1);
return LastOpcFiltered;
}
+
// Return the filter chooser for the group of instructions without constant
// segment values.
const FilterChooser &getVariableFC() const {
@@ -253,11 +272,6 @@
return *(FilterChooserMap.find((unsigned)-1)->second);
}
- Filter(Filter &&f);
- Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed);
-
- ~Filter();
-
// Divides the decoding task into sub tasks and delegates them to the
// inferior FilterChooser's.
//
@@ -273,8 +287,9 @@
// Returns the number of fanout produced by the filter. More fanout implies
// the filter distinguishes more categories of instructions.
unsigned usefulness() const;
-}; // End of class Filter
-} // End anonymous namespace
+}; // end class Filter
+
+} // end anonymous namespace
// These are states of our finite state machines used in FilterChooser's
// filterProcessor() which produces the filter candidates to use.
@@ -302,6 +317,7 @@
/// decoding tree. And each case is delegated to an inferior FilterChooser to
/// decide what further remaining bits to look at.
namespace {
+
class FilterChooser {
protected:
friend class Filter;
@@ -313,7 +329,7 @@
const std::vector<unsigned> &Opcodes;
// Lookup table for the operand decoding of instructions.
- const std::map<unsigned, std::vector<OperandInfo> > &Operands;
+ const std::map<unsigned, std::vector<OperandInfo>> &Operands;
// Vector of candidate filters.
std::vector<Filter> Filters;
@@ -334,16 +350,13 @@
// Parent emitter
const FixedLenDecoderEmitter *Emitter;
- FilterChooser(const FilterChooser &) = delete;
- void operator=(const FilterChooser &) = delete;
public:
-
FilterChooser(ArrayRef<const CodeGenInstruction *> Insts,
const std::vector<unsigned> &IDs,
- const std::map<unsigned, std::vector<OperandInfo> > &Ops,
+ const std::map<unsigned, std::vector<OperandInfo>> &Ops,
unsigned BW,
const FixedLenDecoderEmitter *E)
- : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
+ : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
FilterBitValues(BW, BIT_UNFILTERED), Parent(nullptr), BestIndex(-1),
BitWidth(BW), Emitter(E) {
doFilter();
@@ -351,16 +364,18 @@
FilterChooser(ArrayRef<const CodeGenInstruction *> Insts,
const std::vector<unsigned> &IDs,
- const std::map<unsigned, std::vector<OperandInfo> > &Ops,
+ const std::map<unsigned, std::vector<OperandInfo>> &Ops,
const std::vector<bit_value_t> &ParentFilterBitValues,
const FilterChooser &parent)
: AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
- Filters(), FilterBitValues(ParentFilterBitValues),
- Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth),
- Emitter(parent.Emitter) {
+ FilterBitValues(ParentFilterBitValues), Parent(&parent), BestIndex(-1),
+ BitWidth(parent.BitWidth), Emitter(parent.Emitter) {
doFilter();
}
+ FilterChooser(const FilterChooser &) = delete;
+ void operator=(const FilterChooser &) = delete;
+
unsigned getBitWidth() const { return BitWidth; }
protected:
@@ -477,7 +492,8 @@
// instructions.
void emitTableEntries(DecoderTableInfo &TableInfo) const;
};
-} // End anonymous namespace
+
+} // end anonymous namespace
///////////////////////////
// //
@@ -528,9 +544,6 @@
&& "Filter returns no instruction categories");
}
-Filter::~Filter() {
-}
-
// Divides the decoding task into sub tasks and delegates them to the
// inferior FilterChooser's.
//
@@ -1072,7 +1085,7 @@
for (const auto &Op : Operands.find(Opc)->second) {
// If a custom instruction decoder was specified, use that.
- if (Op.numFields() == 0 && Op.Decoder.size()) {
+ if (Op.numFields() == 0 && !Op.Decoder.empty()) {
HasCompleteDecoder = Op.HasCompleteDecoder;
OS.indent(Indentation) << Emitter->GuardPrefix << Op.Decoder
<< "(MI, insn, Address, Decoder)"
@@ -1142,7 +1155,7 @@
StringRef SR(P);
std::pair<StringRef, StringRef> pairs = SR.split(',');
- while (pairs.second.size()) {
+ while (!pairs.second.empty()) {
emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
o << " && ";
pairs = pairs.second.split(',');
@@ -1371,7 +1384,6 @@
Best.getVariableFC().emitTableEntries(TableInfo);
}
-
// Assign a single filter and run with it. Top level API client can initialize
// with a single filter to start the filtering process.
void FilterChooser::runSingleFilter(unsigned startBit, unsigned numBit,
@@ -1719,7 +1731,7 @@
static bool populateInstruction(CodeGenTarget &Target,
const CodeGenInstruction &CGI, unsigned Opc,
- std::map<unsigned, std::vector<OperandInfo> > &Operands){
+ std::map<unsigned, std::vector<OperandInfo>> &Operands){
const Record &Def = *CGI.TheDef;
// If all the bit positions are not specified; do not decode this instruction.
// We are bound to fail! For proper disassembly, the well-known encoding bits
@@ -1747,7 +1759,7 @@
// Gather the outputs/inputs of the instruction, so we can find their
// positions in the encoding. This assumes for now that they appear in the
// MCInst in the order that they're listed.
- std::vector<std::pair<Init*, std::string> > InOutOperands;
+ std::vector<std::pair<Init*, std::string>> InOutOperands;
DagInit *Out = Def.getValueAsDag("OutOperandList");
DagInit *In = Def.getValueAsDag("InOperandList");
for (unsigned i = 0; i < Out->getNumArgs(); ++i)
@@ -1768,7 +1780,7 @@
}
}
- std::map<std::string, std::vector<OperandInfo> > NumberedInsnOperands;
+ std::map<std::string, std::vector<OperandInfo>> NumberedInsnOperands;
std::set<std::string> NumberedInsnOperandsNoTie;
if (Target.getInstructionSet()->
getValueAsBit("decodePositionallyEncodedOperands")) {
@@ -1853,7 +1865,7 @@
Name << "(" << SO.first << ", " << SO.second << ") => " <<
Vals[i].getName() << "\n");
- std::string Decoder = "";
+ std::string Decoder;
Record *TypeRecord = CGI.Operands[SO.first].Rec;
RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod");
@@ -2014,7 +2026,6 @@
Operands[Opc] = InsnOperands;
-
#if 0
DEBUG({
// Dumps the instruction encoding bits.
@@ -2067,7 +2078,7 @@
<< " const uint8_t *Ptr = DecodeTable;\n"
<< " uint32_t CurFieldValue = 0;\n"
<< " DecodeStatus S = MCDisassembler::Success;\n"
- << " for (;;) {\n"
+ << " while (true) {\n"
<< " ptrdiff_t Loc = Ptr - DecodeTable;\n"
<< " switch (*Ptr) {\n"
<< " default:\n"
@@ -2235,8 +2246,8 @@
// Parameterize the decoders based on namespace and instruction width.
NumberedInstructions = Target.getInstructionsByEnumValue();
std::map<std::pair<std::string, unsigned>,
- std::vector<unsigned> > OpcMap;
- std::map<unsigned, std::vector<OperandInfo> > Operands;
+ std::vector<unsigned>> OpcMap;
+ std::map<unsigned, std::vector<OperandInfo>> Operands;
for (unsigned i = 0; i < NumberedInstructions.size(); ++i) {
const CodeGenInstruction *Inst = NumberedInstructions[i];
@@ -2309,4 +2320,4 @@
ROK, RFail, L).run(OS);
}
-} // End llvm namespace
+} // end namespace llvm