commit a42a54258ec9ad0dbdf876fc05c2ff2d70e46fb3
author Simon Pilgrim <llvm-dev@redking.me.uk> Sat Dec 09 23:42:56 2017 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Sat Dec 09 23:42:56 2017 +0000
tree 57eac9985bc18e7eee01cc21abf702195445204f
parent 70dbd5fbd0a5f869126a944ae7e23058a106f8b7

[InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)

Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)

llvm-svn: 320270

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 7d5d28f..a2e757c 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -435,12 +435,11 @@
     const APInt *SA;
     if (match(I->getOperand(1), m_APInt(SA))) {
       const APInt *ShrAmt;
-      if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt)))) {
-        Instruction *Shr = cast<Instruction>(I->getOperand(0));
-        if (Value *R = simplifyShrShlDemandedBits(
-                Shr, *ShrAmt, I, *SA, DemandedMask, Known))
-          return R;
-      }
+      if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt))))
+        if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
+          if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
+                                                    DemandedMask, Known))
+            return R;
 
       uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
       APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));