commit a4305cec939d0895b97acd45d22e84b561e27d10
author Dan Gohman <gohman@apple.com> Wed Aug 20 21:10:53 2008 +0000
committer Dan Gohman <gohman@apple.com> Wed Aug 20 21:10:53 2008 +0000
tree 6ef92c3cd9e621dbaafe48ae8dbe9f98bae9fd91
parent 02c84b8910687c9145182339999393d577293960

Simplify the BuildMI calls even more.

llvm-svn: 55077

llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 70e0248..b8e5d2c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -155,8 +155,7 @@
   unsigned ResultReg = MRI.createVirtualRegister(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(MF, II, ResultReg);
-  MBB->push_back(MI);
+  MachineInstr *MI = BuildMI(MBB, II, ResultReg);
   return ResultReg;
 }
 
@@ -166,8 +165,7 @@
   unsigned ResultReg = MRI.createVirtualRegister(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0);
-  MBB->push_back(MI);
+  MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0);
   return ResultReg;
 }
 
@@ -177,7 +175,6 @@
   unsigned ResultReg = MRI.createVirtualRegister(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0).addReg(Op1);
-  MBB->push_back(MI);
+  MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
   return ResultReg;
 }