Add support of RDSEED defined in AVX2 extension
llvm-svn: 178314
diff --git a/llvm/test/CodeGen/X86/bool-simplify.ll b/llvm/test/CodeGen/X86/bool-simplify.ll
index 6d8e7fb..fa6f6e8 100644
--- a/llvm/test/CodeGen/X86/bool-simplify.ll
+++ b/llvm/test/CodeGen/X86/bool-simplify.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand,+rdseed | FileCheck %s
define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
@@ -84,7 +84,55 @@
; CHECK: ret
}
+define i16 @seed16(i16 %arg) nounwind uwtable {
+ %1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind
+ %2 = extractvalue { i16, i32 } %1, 0
+ %3 = extractvalue { i16, i32 } %1, 1
+ %4 = icmp eq i32 %3, 0
+ %5 = select i1 %4, i16 0, i16 %arg
+ %6 = add i16 %5, %2
+ ret i16 %6
+; CHECK: seed16
+; CHECK: rdseed
+; CHECK: cmov
+; CHECK-NOT: cmov
+; CHECK: ret
+}
+
+define i32 @seed32(i32 %arg) nounwind uwtable {
+ %1 = tail call { i32, i32 } @llvm.x86.rdseed.32() nounwind
+ %2 = extractvalue { i32, i32 } %1, 0
+ %3 = extractvalue { i32, i32 } %1, 1
+ %4 = icmp eq i32 %3, 0
+ %5 = select i1 %4, i32 0, i32 %arg
+ %6 = add i32 %5, %2
+ ret i32 %6
+; CHECK: seed32
+; CHECK: rdseed
+; CHECK: cmov
+; CHECK-NOT: cmov
+; CHECK: ret
+}
+
+define i64 @seed64(i64 %arg) nounwind uwtable {
+ %1 = tail call { i64, i32 } @llvm.x86.rdseed.64() nounwind
+ %2 = extractvalue { i64, i32 } %1, 0
+ %3 = extractvalue { i64, i32 } %1, 1
+ %4 = icmp eq i32 %3, 0
+ %5 = select i1 %4, i64 0, i64 %arg
+ %6 = add i64 %5, %2
+ ret i64 %6
+; CHECK: seed64
+; CHECK: rdseed
+; CHECK: cmov
+; CHECK-NOT: cmov
+; CHECK: ret
+}
+
declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
declare { i16, i32 } @llvm.x86.rdrand.16() nounwind
declare { i32, i32 } @llvm.x86.rdrand.32() nounwind
declare { i64, i32 } @llvm.x86.rdrand.64() nounwind
+declare { i16, i32 } @llvm.x86.rdseed.16() nounwind
+declare { i32, i32 } @llvm.x86.rdseed.32() nounwind
+declare { i64, i32 } @llvm.x86.rdseed.64() nounwind
diff --git a/llvm/test/CodeGen/X86/rdseed.ll b/llvm/test/CodeGen/X86/rdseed.ll
new file mode 100644
index 0000000..35de7eb
--- /dev/null
+++ b/llvm/test/CodeGen/X86/rdseed.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86-64 -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s
+
+declare {i16, i32} @llvm.x86.rdseed.16()
+declare {i32, i32} @llvm.x86.rdseed.32()
+declare {i64, i32} @llvm.x86.rdseed.64()
+
+define i32 @_rdseed16_step(i16* %random_val) {
+ %call = call {i16, i32} @llvm.x86.rdseed.16()
+ %randval = extractvalue {i16, i32} %call, 0
+ store i16 %randval, i16* %random_val
+ %isvalid = extractvalue {i16, i32} %call, 1
+ ret i32 %isvalid
+; CHECK: _rdseed16_step:
+; CHECK: rdseedw %ax
+; CHECK: movw %ax, (%r[[A0:di|cx]])
+; CHECK: movzwl %ax, %ecx
+; CHECK: movl $1, %eax
+; CHECK: cmovael %ecx, %eax
+; CHECK: ret
+}
+
+define i32 @_rdseed32_step(i32* %random_val) {
+ %call = call {i32, i32} @llvm.x86.rdseed.32()
+ %randval = extractvalue {i32, i32} %call, 0
+ store i32 %randval, i32* %random_val
+ %isvalid = extractvalue {i32, i32} %call, 1
+ ret i32 %isvalid
+; CHECK: _rdseed32_step:
+; CHECK: rdseedl %e[[T0:[a-z]+]]
+; CHECK: movl %e[[T0]], (%r[[A0]])
+; CHECK: movl $1, %eax
+; CHECK: cmovael %e[[T0]], %eax
+; CHECK: ret
+}
+
+define i32 @_rdseed64_step(i64* %random_val) {
+ %call = call {i64, i32} @llvm.x86.rdseed.64()
+ %randval = extractvalue {i64, i32} %call, 0
+ store i64 %randval, i64* %random_val
+ %isvalid = extractvalue {i64, i32} %call, 1
+ ret i32 %isvalid
+; CHECK: _rdseed64_step:
+; CHECK: rdseedq %r[[T1:[a-z]+]]
+; CHECK: movq %r[[T1]], (%r[[A0]])
+; CHECK: movl $1, %eax
+; CHECK: cmovael %e[[T1]], %eax
+; CHECK: ret
+}