[RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884
llvm-svn: 371810
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index ad19741..7d48634 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -74,7 +74,7 @@
.addReg(SrcReg)
.addImm(Val)
.setMIFlag(Flag);
- } else if (isInt<32>(Val)) {
+ } else {
unsigned Opc = RISCV::ADD;
bool isSub = Val < 0;
if (isSub) {
@@ -83,13 +83,11 @@
}
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
+ TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
.addReg(SrcReg)
.addReg(ScratchReg, RegState::Kill)
.setMIFlag(Flag);
- } else {
- report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 46ace19..a71b875 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -14,6 +14,7 @@
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
+#include "Utils/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -156,24 +157,43 @@
BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
}
-void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag) const {
- assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
+void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DstReg, uint64_t Val,
+ MachineInstr::MIFlag Flag) const {
+ MachineFunction *MF = MBB.getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
+ Register SrcReg = RISCV::X0;
+ Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ unsigned Num = 0;
- // TODO: If the value can be materialized using only one instruction, only
- // insert a single instruction.
+ if (!IsRV64 && !isInt<32>(Val))
+ report_fatal_error("Should only materialize 32-bit constants for RV32");
- uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
- uint64_t Lo12 = SignExtend64<12>(Val);
- BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
- .addImm(Hi20)
- .setMIFlag(Flag);
- BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(DstReg, RegState::Kill)
- .addImm(Lo12)
- .setMIFlag(Flag);
+ RISCVMatInt::InstSeq Seq;
+ RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
+ assert(Seq.size() > 0);
+
+ for (RISCVMatInt::Inst &Inst : Seq) {
+ // Write the final result to DstReg if it's the last instruction in the Seq.
+ // Otherwise, write the result to the temp register.
+ if (++Num == Seq.size())
+ Result = DstReg;
+
+ if (Inst.Opc == RISCV::LUI) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
+ .addImm(Inst.Imm)
+ .setMIFlag(Flag);
+ } else {
+ BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
+ .addReg(SrcReg, RegState::Kill)
+ .addImm(Inst.Imm)
+ .setMIFlag(Flag);
+ }
+ // Only the first instruction has X0 as its source.
+ SrcReg = Result;
+ }
}
// The contents of values added to Cond are not examined outside of
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 141fe30..fa930dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -46,10 +46,10 @@
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
- // Materializes the given int32 Val into DstReg.
- void movImm32(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, Register DstReg, uint64_t Val,
- MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
+ // Materializes the given integer Val into DstReg.
+ void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DstReg, uint64_t Val,
+ MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 2bbce25..aa6d06d 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -110,7 +110,7 @@
// The offset won't fit in an immediate, so use a scratch register instead
// Modify Offset and FrameReg appropriately
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm32(MBB, II, DL, ScratchReg, Offset);
+ TII->movImm(MBB, II, DL, ScratchReg, Offset);
BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
.addReg(FrameReg)
.addReg(ScratchReg, RegState::Kill);