AMDGPU: Remove old intrinsic uses
llvm-svn: 303305
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
index 7ca2612..d0276a3 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
@@ -5,7 +5,7 @@
define spir_kernel void @hoge() {
bb:
- %tmp = tail call i32 @llvm.r600.read.tidig.x()
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
br i1 undef, label %bb2, label %bb23
bb2:
@@ -50,4 +50,4 @@
ret void
}
-declare i32 @llvm.r600.read.tidig.x()
+declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll b/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
index bd861e0..3ae74ab 100644
--- a/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
+++ b/llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s
; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
; loop block. This intrinsic will be lowered to s_or_b64 by the code
@@ -14,7 +14,7 @@
; CHECK: s_cbranch_execnz [[LOOP_LABEL]]
define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
entry:
- %cond = call i32 @llvm.r600.read.tidig.x() #0
+ %cond = call i32 @llvm.amdgcn.workitem.id.x() #0
%tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %if, label %loop
@@ -34,6 +34,6 @@
ret void
}
-declare i32 @llvm.r600.read.tidig.x() #0
+declare i32 @llvm.amdgcn.workitem.id.x() #0
-attributes #0 = { readnone }
+attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
index b160af8..4a0213d 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-copy-phi.ll
@@ -12,7 +12,7 @@
; SI: s_endpgm
define amdgpu_kernel void @br_i1_phi(i32 %arg) {
bb:
- %tidig = call i32 @llvm.r600.read.tidig.x() #0
+ %tidig = call i32 @llvm.amdgcn.workitem.id.x()
%cmp = trunc i32 %tidig to i1
br i1 %cmp, label %bb2, label %bb3
@@ -32,6 +32,6 @@
ret void
}
-declare i32 @llvm.r600.read.tidig.x() #0
+declare i32 @llvm.amdgcn.workitem.id.x() #0
-attributes #0 = { readnone }
+attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
index 5f8ca28..1b937ab 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
@@ -7,14 +7,13 @@
; GFX9: flat_store_dword
; GFX9-NOT: s_waitcnt
; GCN: s_barrier
-define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out, i32 %size) #0 {
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp
store i32 %tmp, i32 addrspace(1)* %tmp1
call void @llvm.amdgcn.s.barrier()
- %tmp2 = call i32 @llvm.r600.read.local.size.x()
- %tmp3 = sub i32 %tmp2, 1
+ %tmp3 = sub i32 %size, 1
%tmp4 = sub i32 %tmp3, %tmp
%tmp5 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp4
%tmp6 = load i32, i32 addrspace(1)* %tmp5
@@ -24,7 +23,6 @@
declare void @llvm.amdgcn.s.barrier() #1
declare i32 @llvm.amdgcn.workitem.id.x() #2
-declare i32 @llvm.r600.read.local.size.x() #2
attributes #0 = { nounwind }
attributes #1 = { convergent nounwind }
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
index e82e548..135f02a 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
@@ -186,7 +186,7 @@
%tmp140 = phi float [ 0.000000e+00, %bb ], [ %tmp405, %bb145 ]
%tmp141 = phi float [ 0.000000e+00, %bb ], [ %tmp406, %bb145 ]
%tmp142 = bitcast float %tmp95 to i32
- %tid = call i32 @llvm.r600.read.tidig.x() #1
+ %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%tmp143 = icmp sgt i32 %tmp142, %tid
br i1 %tmp143, label %bb144, label %bb145
@@ -593,7 +593,7 @@
br label %bb12
}
-declare i32 @llvm.r600.read.tidig.x() #1
+declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }