[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.
llvm-svn: 286377
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 2f08cfc..5c1c22f 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -116,8 +116,8 @@
static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
- return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
- isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
+ return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
+ isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
}
@@ -821,9 +821,11 @@
return;
}
if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
+ unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
+ .addReg(HiSrc, KillFlag)
+ .addReg(LoSrc, KillFlag);
return;
}
if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
@@ -843,12 +845,14 @@
return;
}
if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
- unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
- BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag);
- unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg);
- BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstLo)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
+ unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
+ unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
+ unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
+ .addReg(HiSrc, KillFlag);
+ BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
+ .addReg(LoSrc, KillFlag);
return;
}
@@ -1031,8 +1035,8 @@
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), Kill)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), Kill);
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
MBB.erase(MI);
return true;
}
@@ -1040,7 +1044,7 @@
case Hexagon::V6_lo: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
+ unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
MBB.erase(MI);
MRI.clearKillFlags(SrcSubLo);
@@ -1050,7 +1054,7 @@
case Hexagon::V6_hi: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
+ unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
MBB.erase(MI);
MRI.clearKillFlags(SrcSubHi);
@@ -1065,8 +1069,8 @@
bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
Opc == Hexagon::PS_vstorerw_ai_128B);
unsigned SrcReg = MI.getOperand(2).getReg();
- unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
- unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
+ unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
unsigned NewOpc;
if (Aligned)
NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
@@ -1112,12 +1116,12 @@
unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
MachineInstr *MI1New =
BuildMI(MBB, MI, DL, get(NewOpc),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::vsub_lo))
.addOperand(MI.getOperand(1))
.addImm(MI.getOperand(2).getImm());
MI1New->getOperand(1).setIsKill(false);
BuildMI(MBB, MI, DL, get(NewOpc),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::vsub_hi))
.addOperand(MI.getOperand(1))
// The Vectors are indexed in multiples of vector size.
.addImm(MI.getOperand(2).getImm() + Offset)
@@ -1146,16 +1150,16 @@
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Src1Reg = MI.getOperand(1).getReg();
unsigned Src2Reg = MI.getOperand(2).getReg();
- unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
- unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
- unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
- unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
+ unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
+ unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
+ unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
+ unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::isub_hi))
.addReg(Src1SubHi)
.addReg(Src2SubHi);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::isub_lo))
.addReg(Src1SubLo)
.addReg(Src2SubLo);
MBB.erase(MI);
@@ -1171,19 +1175,19 @@
unsigned Src1Reg = MI.getOperand(1).getReg();
unsigned Src2Reg = MI.getOperand(2).getReg();
unsigned Src3Reg = MI.getOperand(3).getReg();
- unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
- unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
- unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
- unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
- unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
- unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
+ unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
+ unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
+ unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
+ unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
+ unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
+ unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::isub_hi))
.addReg(Src1SubHi)
.addReg(Src2SubHi)
.addReg(Src3SubHi);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::isub_lo))
.addReg(Src1SubLo)
.addReg(Src2SubLo)
.addReg(Src3SubLo);
@@ -1260,8 +1264,8 @@
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
if (Op0.getReg() != Op2.getReg()) {
- unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg);
- unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg);
+ unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
+ unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
.addOperand(Op0)
.addOperand(Op1)
@@ -1272,8 +1276,8 @@
IsDestLive = true;
}
if (Op0.getReg() != Op3.getReg()) {
- unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg);
- unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg);
+ unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
+ unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
.addOperand(Op0)
.addOperand(Op1)