commit a5840c3c39baec957c673cf5e0b257f923480ff3
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jan 22 18:36:06 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jan 22 18:36:06 2019 +0000
tree 81be7447b75dc360db501e81eaf0dc6d91b00600
parent 39508331ef7e9417afc43f634c0ef23eb768d974

Codegen support for atomicrmw fadd/fsub

llvm-svn: 351851

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index b684888..f170bc5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4194,7 +4194,6 @@
   NODE_NAME_CASE(ATOMIC_CMP_SWAP)
   NODE_NAME_CASE(ATOMIC_INC)
   NODE_NAME_CASE(ATOMIC_DEC)
-  NODE_NAME_CASE(ATOMIC_LOAD_FADD)
   NODE_NAME_CASE(ATOMIC_LOAD_FMIN)
   NODE_NAME_CASE(ATOMIC_LOAD_FMAX)
   NODE_NAME_CASE(BUFFER_LOAD)
@@ -4518,7 +4517,12 @@
 
 TargetLowering::AtomicExpansionKind
 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
-  if (RMW->getOperation() == AtomicRMWInst::Nand)
+  switch (RMW->getOperation()) {
+  case AtomicRMWInst::Nand:
+  case AtomicRMWInst::FAdd:
+  case AtomicRMWInst::FSub:
     return AtomicExpansionKind::CmpXChg;
-  return AtomicExpansionKind::None;
+  default:
+    return AtomicExpansionKind::None;
+  }
 }