commit a6322941ffc15275e837435eee7aabba0ca15211
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Apr 30 22:08:23 2019 +0000
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Apr 30 22:08:23 2019 +0000
tree 406ac77d15c962134efbcc2bcc813b514078b1cd
parent c239eda8a0e266abe4530923b116c5c83de07b31

[AMDGPU] gfx1010 VMEM and SMEM implementation

Differential Revision: https://reviews.llvm.org/D61330

llvm-svn: 359621

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index f35c2a1..c0a85498 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -356,7 +356,8 @@
           .add(I.getOperand(0))
           .addImm(0)  // offset
           .addImm(0)  // glc
-          .addImm(0); // slc
+          .addImm(0)  // slc
+          .addImm(0); // dlc
 
 
   // Now that we selected an opcode, we need to constrain the register
@@ -532,7 +533,8 @@
                                .addReg(PtrReg)
                                .addImm(0)  // offset
                                .addImm(0)  // glc
-                               .addImm(0); // slc
+                               .addImm(0)  // slc
+                               .addImm(0); // dlc
 
   bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
   I.eraseFromParent();