commit a6a9c20c23a8a1f2a856da0af667fb9fb457b0be
author Akira Hatanaka <ahatanak@gmail.com> Mon Sep 26 21:55:17 2011 +0000
committer Akira Hatanaka <ahatanak@gmail.com> Mon Sep 26 21:55:17 2011 +0000
tree e1ad488e07bc0f1a76c89b45fdc846915a861808
parent 7b502920eff49c3530f0211523c5296bd467435a

Set register class of a register according to value of HasMips64.

llvm-svn: 140570

llvm/lib/Target/Mips/MipsISelLowering.cpp

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 6ad7724..4578d22 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -2268,7 +2268,7 @@
       else if (RegVT == MVT::f32)
         RC = Mips::FGR32RegisterClass;
       else if (RegVT == MVT::f64)
-        RC = Mips::AFGR64RegisterClass;
+        RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass;
       else
         llvm_unreachable("RegVT not supported by FormalArguments Lowering");