ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
llvm-svn: 136969
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index c669416..2caf548 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -812,8 +812,7 @@
// {3-0} Rm
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
- unsigned Imm = MO1.getImm();
- bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
+ bool isAdd = MO1.getImm() != 0;
return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
}