[mips] Set macros for Octeon+ CPU
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index a08c231..b9ab80d 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -62,7 +62,7 @@
 unsigned MipsTargetInfo::getISARev() const {
   return llvm::StringSwitch<unsigned>(getCPU())
              .Cases("mips32", "mips64", 1)
-             .Cases("mips32r2", "mips64r2", "octeon", 2)
+             .Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
              .Cases("mips32r3", "mips64r3", 3)
              .Cases("mips32r5", "mips64r5", 5)
              .Cases("mips32r6", "mips64r6", 6)
@@ -188,7 +188,10 @@
   Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
 
   Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
-  Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
+  if (CPU == "octeon+")
+    Builder.defineMacro("_MIPS_ARCH_OCTEONP");
+  else
+    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
 
   if (StringRef(CPU).startswith("octeon"))
     Builder.defineMacro("__OCTEON__");