commit a77fe4eef387cfe68f0e7b297be42393fd809cde
author Krzysztof Parzyszek <kparzysz@codeaurora.org> Mon Oct 03 17:14:48 2016 +0000
committer Krzysztof Parzyszek <kparzysz@codeaurora.org> Mon Oct 03 17:14:48 2016 +0000
tree 4b23158215d5cffe1651f00152013c3067bde684
parent 53b000afc2bb54aa5d16b1392c715cbca214bb0c

[RDF] Replace RegisterAliasInfo with target-independent code using lane masks

llvm-svn: 283122

llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index 2ea7003..ac362c6 100644
--- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -587,7 +587,7 @@
     return;
 
   for (auto &R : RDefMap) {
-    auto F = DefM.find(R.first);
+    auto F = DefM.find(R.first.Reg);
     if (F == DefM.end() || F->second.empty())
       continue;
     R.second[IA.Id] = F->second.top()->Id;
@@ -622,8 +622,7 @@
   const auto &TRI = *MF.getSubtarget().getRegisterInfo();
   const TargetOperandInfo TOI(*HII);
 
-  RegisterAliasInfo RAI(TRI);
-  DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, RAI, TOI);
+  DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, TOI);
   G.build();
   DFG = &G;