[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
index 1498356..1e35305 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
@@ -14,7 +14,7 @@
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i64>
store <2 x i64> %2, <2 x i64>* %storeaddr
ret void
@@ -33,7 +33,7 @@
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i16>* %loadaddr
+ %1 = load <2 x i16>, <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i64>
store <2 x i64> %2, <2 x i64>* %storeaddr
ret void
@@ -49,7 +49,7 @@
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i32>
store <2 x i32> %2, <2 x i32>* %storeaddr
ret void
@@ -63,7 +63,7 @@
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <2 x i16>* %loadaddr
+ %1 = load <2 x i16>, <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i32>
store <2 x i32> %2, <2 x i32>* %storeaddr
ret void
@@ -80,7 +80,7 @@
; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
; CHECK-NEXT: bx lr
- %1 = load <2 x i8>* %loadaddr
+ %1 = load <2 x i8>, <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i16>
store <2 x i16> %2, <2 x i16>* %storeaddr
ret void
@@ -95,7 +95,7 @@
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
- %1 = load <4 x i8>* %loadaddr
+ %1 = load <4 x i8>, <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* %storeaddr
ret void
@@ -109,7 +109,7 @@
; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
- %1 = load <4 x i8>* %loadaddr
+ %1 = load <4 x i8>, <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* %storeaddr
ret void