[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
index bc508c8..11842dd 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
@@ -10,7 +10,7 @@
; Function Attrs: nounwind
define void @br() #0 {
entry:
- %0 = load i32* @b, align 4
+ %0 = load i32, i32* @b, align 4
%tobool = icmp eq i32 %0, 0
br i1 %tobool, label %if.end, label %if.then
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
index de5f758..f80cb82 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
@@ -84,13 +84,13 @@
; CHECK-LABEL: cxiiiiconv
; mips32r2-LABEL: cxiiiiconv
; mips32-LABEL: cxiiiiconv
- %0 = load i8* @c1, align 1
+ %0 = load i8, i8* @c1, align 1
%conv = sext i8 %0 to i32
- %1 = load i8* @uc1, align 1
+ %1 = load i8, i8* @uc1, align 1
%conv1 = zext i8 %1 to i32
- %2 = load i16* @s1, align 2
+ %2 = load i16, i16* @s1, align 2
%conv2 = sext i16 %2 to i32
- %3 = load i16* @us1, align 2
+ %3 = load i16, i16* @us1, align 2
%conv3 = zext i16 %3 to i32
call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
index 4cbfe00..72de888 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
@@ -12,8 +12,8 @@
; Function Attrs: nounwind
define void @feq1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp oeq float %0, %1
; CHECK-LABEL: feq1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -33,8 +33,8 @@
; Function Attrs: nounwind
define void @fne1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp une float %0, %1
; CHECK-LABEL: fne1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -53,8 +53,8 @@
; Function Attrs: nounwind
define void @flt1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp olt float %0, %1
; CHECK-LABEL: flt1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -74,8 +74,8 @@
; Function Attrs: nounwind
define void @fgt1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp ogt float %0, %1
; CHECK-LABEL: fgt1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -94,8 +94,8 @@
; Function Attrs: nounwind
define void @fle1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp ole float %0, %1
; CHECK-LABEL: fle1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -114,8 +114,8 @@
; Function Attrs: nounwind
define void @fge1() {
entry:
- %0 = load float* @f1, align 4
- %1 = load float* @f2, align 4
+ %0 = load float, float* @f1, align 4
+ %1 = load float, float* @f2, align 4
%cmp = fcmp oge float %0, %1
; CHECK-LABEL: fge1:
; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
@@ -134,8 +134,8 @@
; Function Attrs: nounwind
define void @deq1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp oeq double %0, %1
; CHECK-LABEL: deq1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -154,8 +154,8 @@
; Function Attrs: nounwind
define void @dne1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp une double %0, %1
; CHECK-LABEL: dne1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -174,8 +174,8 @@
; Function Attrs: nounwind
define void @dlt1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp olt double %0, %1
; CHECK-LABEL: dlt1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -194,8 +194,8 @@
; Function Attrs: nounwind
define void @dgt1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp ogt double %0, %1
; CHECK-LABEL: dgt1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -214,8 +214,8 @@
; Function Attrs: nounwind
define void @dle1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp ole double %0, %1
; CHECK-LABEL: dle1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
@@ -234,8 +234,8 @@
; Function Attrs: nounwind
define void @dge1() {
entry:
- %0 = load double* @d1, align 8
- %1 = load double* @d2, align 8
+ %0 = load double, double* @d1, align 8
+ %1 = load double, double* @d2, align 8
%cmp = fcmp oge double %0, %1
; CHECK-LABEL: dge1:
; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
index 8b2570a..5ac2249 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
@@ -10,7 +10,7 @@
; Function Attrs: nounwind
define void @dv() #0 {
entry:
- %0 = load float* @f, align 4
+ %0 = load float, float* @f, align 4
%conv = fpext float %0 to double
; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
store double %conv, double* @d_f, align 8
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
index 5a2cd78..a94ef50 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
@@ -14,7 +14,7 @@
define void @ifv() {
entry:
; CHECK-LABEL: .ent ifv
- %0 = load float* @f, align 4
+ %0 = load float, float* @f, align 4
%conv = fptosi float %0 to i32
; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}}
; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
@@ -26,7 +26,7 @@
define void @idv() {
entry:
; CHECK-LABEL: .ent idv
- %0 = load double* @d, align 8
+ %0 = load double, double* @d, align 8
%conv = fptosi double %0 to i32
; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}}
; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
index f9739e1..2eec4c3 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
@@ -10,7 +10,7 @@
; Function Attrs: nounwind
define void @fv() #0 {
entry:
- %0 = load double* @d, align 8
+ %0 = load double, double* @d, align 8
%conv = fptrunc double %0 to float
; CHECK: cvt.s.d $f{{[0-9]+}}, $f{{[0-9]+}}
store float %conv, float* @f, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
index d2bca3a..670a8d5 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
@@ -14,8 +14,8 @@
entry:
; CHECK-LABEL: .ent eq
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp eq i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -35,8 +35,8 @@
define void @ne() {
entry:
; CHECK-LABEL: .ent ne
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp ne i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -56,8 +56,8 @@
define void @ugt() {
entry:
; CHECK-LABEL: .ent ugt
- %0 = load i32* @uc, align 4
- %1 = load i32* @ud, align 4
+ %0 = load i32, i32* @uc, align 4
+ %1 = load i32, i32* @ud, align 4
%cmp = icmp ugt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -76,8 +76,8 @@
define void @ult() {
entry:
; CHECK-LABEL: .ent ult
- %0 = load i32* @uc, align 4
- %1 = load i32* @ud, align 4
+ %0 = load i32, i32* @uc, align 4
+ %1 = load i32, i32* @ud, align 4
%cmp = icmp ult i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -95,8 +95,8 @@
define void @uge() {
entry:
; CHECK-LABEL: .ent uge
- %0 = load i32* @uc, align 4
- %1 = load i32* @ud, align 4
+ %0 = load i32, i32* @uc, align 4
+ %1 = load i32, i32* @ud, align 4
%cmp = icmp uge i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -115,8 +115,8 @@
define void @ule() {
entry:
; CHECK-LABEL: .ent ule
- %0 = load i32* @uc, align 4
- %1 = load i32* @ud, align 4
+ %0 = load i32, i32* @uc, align 4
+ %1 = load i32, i32* @ud, align 4
%cmp = icmp ule i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
@@ -135,8 +135,8 @@
define void @sgt() {
entry:
; CHECK-LABEL: .ent sgt
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp sgt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -154,8 +154,8 @@
define void @slt() {
entry:
; CHECK-LABEL: .ent slt
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp slt i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
@@ -173,8 +173,8 @@
define void @sge() {
entry:
; CHECK-LABEL: .ent sge
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp sge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @b1, align 4
@@ -193,8 +193,8 @@
define void @sle() {
entry:
; CHECK-LABEL: .ent sle
- %0 = load i32* @c, align 4
- %1 = load i32* @d, align 4
+ %0 = load i32, i32* @c, align 4
+ %1 = load i32, i32* @d, align 4
%cmp = icmp sle i32 %0, %1
%conv = zext i1 %cmp to i32
; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
index c649f61..3daf03d 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
@@ -21,7 +21,7 @@
; Function Attrs: nounwind
define void @cfoo() #0 {
entry:
- %0 = load i8* @c2, align 1
+ %0 = load i8, i8* @c2, align 1
store i8 %0, i8* @c1, align 1
; CHECK-LABEL: cfoo:
; CHECK: lbu $[[REGc:[0-9]+]], 0(${{[0-9]+}})
@@ -34,7 +34,7 @@
; Function Attrs: nounwind
define void @sfoo() #0 {
entry:
- %0 = load i16* @s2, align 2
+ %0 = load i16, i16* @s2, align 2
store i16 %0, i16* @s1, align 2
; CHECK-LABEL: sfoo:
; CHECK: lhu $[[REGs:[0-9]+]], 0(${{[0-9]+}})
@@ -46,7 +46,7 @@
; Function Attrs: nounwind
define void @ifoo() #0 {
entry:
- %0 = load i32* @i2, align 4
+ %0 = load i32, i32* @i2, align 4
store i32 %0, i32* @i1, align 4
; CHECK-LABEL: ifoo:
; CHECK: lw $[[REGi:[0-9]+]], 0(${{[0-9]+}})
@@ -58,7 +58,7 @@
; Function Attrs: nounwind
define void @ffoo() #0 {
entry:
- %0 = load float* @f2, align 4
+ %0 = load float, float* @f2, align 4
store float %0, float* @f1, align 4
; CHECK-LABEL: ffoo:
; CHECK: lwc1 $f[[REGf:[0-9]+]], 0(${{[0-9]+}})
@@ -71,7 +71,7 @@
; Function Attrs: nounwind
define void @dfoo() #0 {
entry:
- %0 = load double* @d2, align 8
+ %0 = load double, double* @d2, align 8
store double %0, double* @d1, align 8
; CHECK-LABEL: dfoo:
; CHECK: ldc1 $f[[REGd:[0-9]+]], 0(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
index ca56520..acba132 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
@@ -28,11 +28,11 @@
define void @_Z3b_iv() {
entry:
; CHECK-LABEL: .ent _Z3b_iv
- %0 = load i8* @b1, align 1
+ %0 = load i8, i8* @b1, align 1
%tobool = trunc i8 %0 to i1
%frombool = zext i1 %tobool to i8
store i8 %frombool, i8* @b2, align 1
- %1 = load i8* @b2, align 1
+ %1 = load i8, i8* @b2, align 1
%tobool1 = trunc i8 %1 to i1
%conv = zext i1 %tobool1 to i32
store i32 %conv, i32* @i, align 4
@@ -51,10 +51,10 @@
entry:
; CHECK-LABEL: .ent _Z4uc_iv
- %0 = load i8* @uc1, align 1
+ %0 = load i8, i8* @uc1, align 1
%conv = zext i8 %0 to i32
store i32 %conv, i32* @i, align 4
- %1 = load i8* @uc2, align 1
+ %1 = load i8, i8* @uc2, align 1
%conv1 = zext i8 %1 to i32
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
@@ -71,10 +71,10 @@
; mips32r2-LABEL: .ent _Z4sc_iv
; mips32-LABEL: .ent _Z4sc_iv
- %0 = load i8* @sc1, align 1
+ %0 = load i8, i8* @sc1, align 1
%conv = sext i8 %0 to i32
store i32 %conv, i32* @i, align 4
- %1 = load i8* @sc2, align 1
+ %1 = load i8, i8* @sc2, align 1
%conv1 = sext i8 %1 to i32
store i32 %conv1, i32* @j, align 4
; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
@@ -91,10 +91,10 @@
define void @_Z4us_iv() {
entry:
; CHECK-LABEL: .ent _Z4us_iv
- %0 = load i16* @us1, align 2
+ %0 = load i16, i16* @us1, align 2
%conv = zext i16 %0 to i32
store i32 %conv, i32* @i, align 4
- %1 = load i16* @us2, align 2
+ %1 = load i16, i16* @us2, align 2
%conv1 = zext i16 %1 to i32
store i32 %conv1, i32* @j, align 4
ret void
@@ -109,10 +109,10 @@
; mips32r2-LABEL: .ent _Z4ss_iv
; mips32=LABEL: .ent _Z4ss_iv
- %0 = load i16* @ss1, align 2
+ %0 = load i16, i16* @ss1, align 2
%conv = sext i16 %0 to i32
store i32 %conv, i32* @i, align 4
- %1 = load i16* @ss2, align 2
+ %1 = load i16, i16* @ss2, align 2
%conv1 = sext i16 %1 to i32
store i32 %conv1, i32* @j, align 4
; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
@@ -129,7 +129,7 @@
define void @_Z4b_ssv() {
entry:
; CHECK-LABEL: .ent _Z4b_ssv
- %0 = load i8* @b2, align 1
+ %0 = load i8, i8* @b2, align 1
%tobool = trunc i8 %0 to i1
%conv = zext i1 %tobool to i16
store i16 %conv, i16* @ssi, align 2
@@ -143,10 +143,10 @@
define void @_Z5uc_ssv() {
entry:
; CHECK-LABEL: .ent _Z5uc_ssv
- %0 = load i8* @uc1, align 1
+ %0 = load i8, i8* @uc1, align 1
%conv = zext i8 %0 to i16
store i16 %conv, i16* @ssi, align 2
- %1 = load i8* @uc2, align 1
+ %1 = load i8, i8* @uc2, align 1
%conv1 = zext i8 %1 to i16
; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
@@ -161,10 +161,10 @@
entry:
; mips32r2-LABEL: .ent _Z5sc_ssv
; mips32-LABEL: .ent _Z5sc_ssv
- %0 = load i8* @sc1, align 1
+ %0 = load i8, i8* @sc1, align 1
%conv = sext i8 %0 to i16
store i16 %conv, i16* @ssi, align 2
- %1 = load i8* @sc2, align 1
+ %1 = load i8, i8* @sc2, align 1
%conv1 = sext i8 %1 to i16
store i16 %conv1, i16* @ssj, align 2
; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
index 3792510..db01362 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
@@ -12,7 +12,7 @@
define void @foo() {
entry:
; CHECK-LABEL: .ent foo
- %0 = load float** @y, align 4
+ %0 = load float*, float** @y, align 4
%arrayidx = getelementptr inbounds float, float* %0, i32 64000
store float 5.500000e+00, float* %arrayidx, align 4
; CHECK: lui $[[REG_FPCONST_INT:[0-9]+]], 16560
@@ -31,9 +31,9 @@
define void @goo() {
entry:
; CHECK-LABEL: .ent goo
- %0 = load float** @y, align 4
+ %0 = load float*, float** @y, align 4
%arrayidx = getelementptr inbounds float, float* %0, i32 64000
- %1 = load float* %arrayidx, align 4
+ %1 = load float, float* %arrayidx, align 4
store float %1, float* @result, align 4
; CHECK-DAG: lw $[[REG_RESULT:[0-9]+]], %got(result)(${{[0-9]+}})
; CHECK-DAG: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
index 109a7f6..ce0ca34 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
@@ -11,7 +11,7 @@
define i32 @reti() {
entry:
; CHECK-LABEL: reti:
- %0 = load i32* @i, align 4
+ %0 = load i32, i32* @i, align 4
ret i32 %0
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
@@ -25,7 +25,7 @@
define signext i16 @rets() {
entry:
; CHECK-LABEL: rets:
- %0 = load i16* @s, align 2
+ %0 = load i16, i16* @s, align 2
ret i16 %0
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
@@ -40,7 +40,7 @@
define signext i8 @retc() {
entry:
; CHECK-LABEL: retc:
- %0 = load i8* @c, align 1
+ %0 = load i8, i8* @c, align 1
ret i8 %0
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
@@ -55,7 +55,7 @@
define float @retf() {
entry:
; CHECK-LABEL: retf:
- %0 = load float* @f, align 4
+ %0 = load float, float* @f, align 4
ret float %0
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
@@ -69,7 +69,7 @@
define double @retd() {
entry:
; CHECK-LABEL: retd:
- %0 = load double* @d, align 8
+ %0 = load double, double* @d, align 8
ret double %0
; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
index 18fd5ac..df1c827 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/shift.ll
@@ -9,7 +9,7 @@
entry:
%foo = alloca %struct.s, align 4
%0 = bitcast %struct.s* %foo to i32*
- %bf.load = load i32* %0, align 4
+ %bf.load = load i32, i32* %0, align 4
%bf.lshr = lshr i32 %bf.load, 2
%cmp = icmp ne i32 %bf.lshr, 2
br i1 %cmp, label %if.then, label %if.end