[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
diff --git a/llvm/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll b/llvm/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
index 777f375..49b5605 100644
--- a/llvm/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
+++ b/llvm/test/Transforms/Mem2Reg/2002-03-28-UninitializedVal.ll
@@ -6,6 +6,6 @@
define i32 @test() {
; To be promoted
%X = alloca i32 ; <i32*> [#uses=1]
- %Y = load i32* %X ; <i32> [#uses=1]
+ %Y = load i32, i32* %X ; <i32> [#uses=1]
ret i32 %Y
}
diff --git a/llvm/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll b/llvm/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
index f5f1ee3..a013ff4 100644
--- a/llvm/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
+++ b/llvm/test/Transforms/Mem2Reg/2003-04-24-MultipleIdenticalSuccessors.ll
@@ -10,7 +10,7 @@
store i32 2, i32* %X
br i1 %c2, label %Exit, label %Exit
Exit: ; preds = %B2, %B2, %0
- %Y = load i32* %X ; <i32> [#uses=1]
+ %Y = load i32, i32* %X ; <i32> [#uses=1]
ret i32 %Y
}
diff --git a/llvm/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll b/llvm/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
index e82caa9..de7280e 100644
--- a/llvm/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
+++ b/llvm/test/Transforms/Mem2Reg/2003-06-26-IterativePromote.ll
@@ -7,10 +7,10 @@
%p = alloca i32* ; <i32**> [#uses=2]
store i32 0, i32* %a
store i32* %a, i32** %p
- %tmp.0 = load i32** %p ; <i32*> [#uses=1]
- %tmp.1 = load i32* %tmp.0 ; <i32> [#uses=1]
+ %tmp.0 = load i32*, i32** %p ; <i32*> [#uses=1]
+ %tmp.1 = load i32, i32* %tmp.0 ; <i32> [#uses=1]
store i32 %tmp.1, i32* %result
- %tmp.2 = load i32* %result ; <i32> [#uses=1]
+ %tmp.2 = load i32, i32* %result ; <i32> [#uses=1]
ret i32 %tmp.2
}
diff --git a/llvm/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll b/llvm/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
index 1d38efc..8d55a1d 100644
--- a/llvm/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
+++ b/llvm/test/Transforms/Mem2Reg/2003-10-05-DeadPHIInsertion.ll
@@ -9,11 +9,11 @@
br i1 %C, label %L1, label %L2
L1: ; preds = %0
store i32 %B, i32* %A
- %D = load i32* %A ; <i32> [#uses=1]
+ %D = load i32, i32* %A ; <i32> [#uses=1]
call void @test( i32 %D, i1 false )
br label %L3
L2: ; preds = %0
- %E = load i32* %A ; <i32> [#uses=1]
+ %E = load i32, i32* %A ; <i32> [#uses=1]
call void @test( i32 %E, i1 true )
br label %L3
L3: ; preds = %L2, %L1
diff --git a/llvm/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll b/llvm/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
index b064b13..f0f1fdc 100644
--- a/llvm/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
+++ b/llvm/test/Transforms/Mem2Reg/2005-06-30-ReadBeforeWrite.ll
@@ -14,31 +14,31 @@
store i32 0, i32* %i
br label %loopentry
loopentry: ; preds = %endif, %entry
- %tmp.0 = load i32* %n_addr ; <i32> [#uses=1]
+ %tmp.0 = load i32, i32* %n_addr ; <i32> [#uses=1]
%tmp.1 = add i32 %tmp.0, 1 ; <i32> [#uses=1]
- %tmp.2 = load i32* %i ; <i32> [#uses=1]
+ %tmp.2 = load i32, i32* %i ; <i32> [#uses=1]
%tmp.3 = icmp sgt i32 %tmp.1, %tmp.2 ; <i1> [#uses=2]
%tmp.4 = zext i1 %tmp.3 to i32 ; <i32> [#uses=0]
br i1 %tmp.3, label %no_exit, label %return
no_exit: ; preds = %loopentry
- %tmp.5 = load i32* %undef ; <i32> [#uses=1]
+ %tmp.5 = load i32, i32* %undef ; <i32> [#uses=1]
store i32 %tmp.5, i32* %out
store i32 0, i32* %undef
- %tmp.6 = load i32* %i ; <i32> [#uses=1]
+ %tmp.6 = load i32, i32* %i ; <i32> [#uses=1]
%tmp.7 = icmp sgt i32 %tmp.6, 0 ; <i1> [#uses=2]
%tmp.8 = zext i1 %tmp.7 to i32 ; <i32> [#uses=0]
br i1 %tmp.7, label %then, label %endif
then: ; preds = %no_exit
- %tmp.9 = load i8** %p_addr ; <i8*> [#uses=1]
- %tmp.10 = load i32* %i ; <i32> [#uses=1]
+ %tmp.9 = load i8*, i8** %p_addr ; <i8*> [#uses=1]
+ %tmp.10 = load i32, i32* %i ; <i32> [#uses=1]
%tmp.11 = sub i32 %tmp.10, 1 ; <i32> [#uses=1]
%tmp.12 = getelementptr i8, i8* %tmp.9, i32 %tmp.11 ; <i8*> [#uses=1]
- %tmp.13 = load i32* %out ; <i32> [#uses=1]
+ %tmp.13 = load i32, i32* %out ; <i32> [#uses=1]
%tmp.14 = trunc i32 %tmp.13 to i8 ; <i8> [#uses=1]
store i8 %tmp.14, i8* %tmp.12
br label %endif
endif: ; preds = %then, %no_exit
- %tmp.15 = load i32* %i ; <i32> [#uses=1]
+ %tmp.15 = load i32, i32* %i ; <i32> [#uses=1]
%inc = add i32 %tmp.15, 1 ; <i32> [#uses=1]
store i32 %inc, i32* %i
br label %loopentry
diff --git a/llvm/test/Transforms/Mem2Reg/2005-11-28-Crash.ll b/llvm/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
index 8fd3351..4b1d7f66 100644
--- a/llvm/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
+++ b/llvm/test/Transforms/Mem2Reg/2005-11-28-Crash.ll
@@ -41,7 +41,7 @@
loopexit: ; preds = %loopentry
br label %endif.4
then.4: ; No predecessors!
- %tmp.61 = load i32* %flags ; <i32> [#uses=0]
+ %tmp.61 = load i32, i32* %flags ; <i32> [#uses=0]
br label %out
dead_block_after_goto: ; No predecessors!
br label %endif.4
diff --git a/llvm/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll b/llvm/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
index ea581d1..812b8b6 100644
--- a/llvm/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
+++ b/llvm/test/Transforms/Mem2Reg/2007-08-27-VolatileLoadsStores.ll
@@ -22,7 +22,7 @@
br i1 %toBool, label %bb, label %bb5
bb: ; preds = %entry
- %tmp4 = load volatile i32* %v, align 4 ; <i32> [#uses=1]
+ %tmp4 = load volatile i32, i32* %v, align 4 ; <i32> [#uses=1]
store i32 %tmp4, i32* %tmp, align 4
br label %bb6
@@ -33,12 +33,12 @@
br label %bb6
bb6: ; preds = %bb5, %bb
- %tmp7 = load i32* %tmp, align 4 ; <i32> [#uses=1]
+ %tmp7 = load i32, i32* %tmp, align 4 ; <i32> [#uses=1]
store i32 %tmp7, i32* %retval, align 4
br label %return
return: ; preds = %bb6
- %retval8 = load i32* %retval ; <i32> [#uses=1]
+ %retval8 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %retval8
}
diff --git a/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo.ll b/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
index a7369c0..16067f5 100644
--- a/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
+++ b/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
@@ -15,18 +15,18 @@
store i32 %i, i32* %i_addr
call void @llvm.dbg.declare(metadata double* %j_addr, metadata !9, metadata !{}), !dbg !8
store double %j, double* %j_addr
- %1 = load i32* %i_addr, align 4, !dbg !10 ; <i32> [#uses=1]
+ %1 = load i32, i32* %i_addr, align 4, !dbg !10 ; <i32> [#uses=1]
%2 = add nsw i32 %1, 1, !dbg !10 ; <i32> [#uses=1]
%3 = sitofp i32 %2 to double, !dbg !10 ; <double> [#uses=1]
- %4 = load double* %j_addr, align 8, !dbg !10 ; <double> [#uses=1]
+ %4 = load double, double* %j_addr, align 8, !dbg !10 ; <double> [#uses=1]
%5 = fadd double %3, %4, !dbg !10 ; <double> [#uses=1]
store double %5, double* %0, align 8, !dbg !10
- %6 = load double* %0, align 8, !dbg !10 ; <double> [#uses=1]
+ %6 = load double, double* %0, align 8, !dbg !10 ; <double> [#uses=1]
store double %6, double* %retval, align 8, !dbg !10
br label %return, !dbg !10
return: ; preds = %entry
- %retval1 = load double* %retval, !dbg !10 ; <double> [#uses=1]
+ %retval1 = load double, double* %retval, !dbg !10 ; <double> [#uses=1]
ret double %retval1, !dbg !10
}
diff --git a/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll b/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
index 76d2a1a..b8543bc 100644
--- a/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
+++ b/llvm/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
@@ -13,16 +13,16 @@
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
call void @llvm.dbg.declare(metadata i32* %a_addr, metadata !0, metadata !{}), !dbg !7
store i32 %a, i32* %a_addr
- %0 = load i32* %a_addr, align 4, !dbg !8 ; <i32> [#uses=1]
+ %0 = load i32, i32* %a_addr, align 4, !dbg !8 ; <i32> [#uses=1]
call void @llvm.dbg.declare(metadata i32* %x_addr.i, metadata !9, metadata !{}) nounwind, !dbg !15
store i32 %0, i32* %x_addr.i
call void @llvm.dbg.declare(metadata i64* %y_addr.i, metadata !16, metadata !{}) nounwind, !dbg !15
store i64 55, i64* %y_addr.i
call void @llvm.dbg.declare(metadata i8** %z_addr.i, metadata !17, metadata !{}) nounwind, !dbg !15
store i8* bitcast (void (i32)* @baz to i8*), i8** %z_addr.i
- %1 = load i32* %x_addr.i, align 4, !dbg !18 ; <i32> [#uses=1]
- %2 = load i64* %y_addr.i, align 8, !dbg !18 ; <i64> [#uses=1]
- %3 = load i8** %z_addr.i, align 8, !dbg !18 ; <i8*> [#uses=1]
+ %1 = load i32, i32* %x_addr.i, align 4, !dbg !18 ; <i32> [#uses=1]
+ %2 = load i64, i64* %y_addr.i, align 8, !dbg !18 ; <i64> [#uses=1]
+ %3 = load i8*, i8** %z_addr.i, align 8, !dbg !18 ; <i8*> [#uses=1]
call void @foo(i32 %1, i64 %2, i8* %3) nounwind, !dbg !18
br label %return, !dbg !19
diff --git a/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll b/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
index 1be6b03..b7f3994 100644
--- a/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
+++ b/llvm/test/Transforms/Mem2Reg/PromoteMemToRegister.ll
@@ -6,12 +6,12 @@
%J = alloca double ; <double*> [#uses=2]
store i32 %i, i32* %I
store double %j, double* %J
- %t1 = load i32* %I ; <i32> [#uses=1]
+ %t1 = load i32, i32* %I ; <i32> [#uses=1]
%t2 = add i32 %t1, 1 ; <i32> [#uses=1]
store i32 %t2, i32* %I
- %t3 = load i32* %I ; <i32> [#uses=1]
+ %t3 = load i32, i32* %I ; <i32> [#uses=1]
%t4 = sitofp i32 %t3 to double ; <double> [#uses=1]
- %t5 = load double* %J ; <double> [#uses=1]
+ %t5 = load double, double* %J ; <double> [#uses=1]
%t6 = fmul double %t4, %t5 ; <double> [#uses=1]
ret double %t6
}
diff --git a/llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll b/llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll
index 5013229..eeeb72f 100644
--- a/llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll
+++ b/llvm/test/Transforms/Mem2Reg/UndefValuesMerge.ll
@@ -7,7 +7,7 @@
store i32 %i, i32* %I
br label %Cont
Cont: ; preds = %T, %0
- %Y = load i32* %I ; <i32> [#uses=1]
+ %Y = load i32, i32* %I ; <i32> [#uses=1]
ret i32 %Y
}
diff --git a/llvm/test/Transforms/Mem2Reg/atomic.ll b/llvm/test/Transforms/Mem2Reg/atomic.ll
index 5bc9e92..f20043d 100644
--- a/llvm/test/Transforms/Mem2Reg/atomic.ll
+++ b/llvm/test/Transforms/Mem2Reg/atomic.ll
@@ -7,6 +7,6 @@
; CHECK: ret i32 %x
%a = alloca i32
store atomic i32 %x, i32* %a seq_cst, align 4
- %r = load atomic i32* %a seq_cst, align 4
+ %r = load atomic i32, i32* %a seq_cst, align 4
ret i32 %r
}
diff --git a/llvm/test/Transforms/Mem2Reg/crash.ll b/llvm/test/Transforms/Mem2Reg/crash.ll
index 59e2c0b..a4a31b1 100644
--- a/llvm/test/Transforms/Mem2Reg/crash.ll
+++ b/llvm/test/Transforms/Mem2Reg/crash.ll
@@ -14,7 +14,7 @@
br label %bb15
bb15:
- %B = load i32* %whichFlag
+ %B = load i32, i32* %whichFlag
ret i32 %B
lpad86:
@@ -33,11 +33,11 @@
br label %bb15
bb15:
- %B = load i32* %whichFlag
+ %B = load i32, i32* %whichFlag
ret i32 %B
invcont2:
- %C = load i32* %whichFlag
+ %C = load i32, i32* %whichFlag
store i32 %C, i32* %whichFlag
br label %bb15
}