commit a79ac14fa68297f9888bc70a10df5ed9b8864e38
author David Blaikie <dblaikie@gmail.com> Fri Feb 27 21:17:42 2015 +0000
committer David Blaikie <dblaikie@gmail.com> Fri Feb 27 21:17:42 2015 +0000
tree 8d8217a8928e3ee599bdde405e2e178b3a55b645
parent 83687fb9e654c9d0086e7f6b728c26fa0b729e71

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794

llvm/test/Transforms/PhaseOrdering/gdce.ll

diff --git a/llvm/test/Transforms/PhaseOrdering/gdce.ll b/llvm/test/Transforms/PhaseOrdering/gdce.ll
index 95f0675..56d5cbc 100644
--- a/llvm/test/Transforms/PhaseOrdering/gdce.ll
+++ b/llvm/test/Transforms/PhaseOrdering/gdce.ll
@@ -27,7 +27,7 @@
   store i32 0, i32* %retval
   store i32 1, i32* %cleanup.dest.slot
   call void @_ZN4BaseD1Ev(%class.Base* %b)
-  %0 = load i32* %retval
+  %0 = load i32, i32* %retval
   ret i32 %0
 }
 
@@ -35,7 +35,7 @@
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   call void @_ZN4BaseC2Ev(%class.Base* %this1)
   ret void
 }
@@ -44,7 +44,7 @@
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   call void @_ZN4BaseD2Ev(%class.Base* %this1)
   ret void
 }
@@ -53,7 +53,7 @@
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   ret void
 }
 
@@ -61,7 +61,7 @@
 entry:
   %this.addr = alloca %class.Base*, align 8
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   %0 = bitcast %class.Base* %this1 to i8***
   store i8** getelementptr inbounds ([4 x i8*]* @_ZTV4Base, i64 0, i64 2), i8*** %0
   ret void
@@ -73,7 +73,7 @@
   %exn.slot = alloca i8*
   %ehselector.slot = alloca i32
   store %class.Base* %this, %class.Base** %this.addr, align 8
-  %this1 = load %class.Base** %this.addr
+  %this1 = load %class.Base*, %class.Base** %this.addr
   invoke void @_ZN4BaseD1Ev(%class.Base* %this1)
           to label %invoke.cont unwind label %lpad
 
@@ -94,8 +94,8 @@
   br label %eh.resume
 
 eh.resume:                                        ; preds = %lpad
-  %exn = load i8** %exn.slot
-  %sel = load i32* %ehselector.slot
+  %exn = load i8*, i8** %exn.slot
+  %sel = load i32, i32* %ehselector.slot
   %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
   %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
   resume { i8*, i32 } %lpad.val2