commit a7cd83bc88b0a8cbd07b3dbe078e11a0a4e9e442
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jan 22 18:53:41 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jan 22 18:53:41 2019 +0000
tree b20ce4c56cdefb23e1667c8ca7e0f161dee3da36
parent 4063cfc7451fb02b52b27e6298703743c7661cdd

GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT

llvm-svn: 351853

llvm/lib/CodeGen/MachineVerifier.cpp

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b7e0f57..ad7825b 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -990,6 +990,16 @@
   switch(MI->getOpcode()) {
   default:
     break;
+  case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_FCONSTANT: {
+    if (MI->getNumOperands() < MCID.getNumOperands())
+      break;
+
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+    if (DstTy.isVector())
+      report("Instruction cannot use a vector result type", MI);
+    break;
+  }
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
     // Generic loads and stores must have a single MachineMemOperand