bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
    mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index afaea04..bd7fa5c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -544,6 +544,24 @@
       Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
   }
 
+  // FIXME: handle tail calls differently.
+  unsigned CallOpc;
+  if (Subtarget->isThumb()) {
+    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
+      CallOpc = ARMISD::CALL_NOLINK;
+    else
+      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
+  } else {
+    CallOpc = (isDirect || Subtarget->hasV5TOps())
+      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
+  }
+  if (CallOpc == ARMISD::CALL_NOLINK) {
+    // On CALL_NOLINK we must move PC to LR
+    Chain = DAG.getCopyToReg(Chain, ARM::LR,
+                             DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+    InFlag = Chain.getValue(1);
+  }
+
   std::vector<MVT::ValueType> NodeTys;
   NodeTys.push_back(MVT::Other);   // Returns a chain
   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
@@ -558,17 +576,6 @@
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
-  // FIXME: handle tail calls differently.
-  unsigned CallOpc;
-  if (Subtarget->isThumb()) {
-    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
-      CallOpc = ARMISD::CALL_NOLINK;
-    else
-      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
-  } else {
-    CallOpc = (isDirect || Subtarget->hasV5TOps())
-      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
-  }
   if (InFlag.Val)
     Ops.push_back(InFlag);
   Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index bb8b61f..201f65c 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -370,8 +370,6 @@
   : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AI4<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AIx2<dag ops, string asm, list<dag> pattern>
-  : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
 class AI1x2<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -546,10 +544,12 @@
   def BLX : AI<(ops GPR:$dst, variable_ops),
                "blx $dst",
                [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
-  // ARMv4T
-  def BX : AIx2<(ops GPR:$dst, variable_ops),
-                "mov lr, pc\n\tbx $dst",
+  let Uses = [LR] in {
+    // ARMv4T
+    def BX : AI<(ops GPR:$dst, variable_ops),
+                "bx $dst",
                 [(ARMcall_nolink GPR:$dst)]>;
+  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 3c7cd03..a1f03bd 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -189,10 +189,12 @@
   def tBLXr : TI<(ops GPR:$dst, variable_ops),
                   "blx $dst",
                   [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
-  // ARMv4T
-  def tBX : TIx2<(ops GPR:$dst, variable_ops),
-                  "cpy lr, pc\n\tbx $dst",
+  let Uses = [LR] in {
+    // ARMv4T
+    def tBX : TI<(ops GPR:$dst, variable_ops),
+                  "bx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
+  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {