[SystemZ] Add z13 vector facility and MC support
This patch adds support for the z13 processor type and its vector facility,
and adds MC support for all new instructions provided by that facilily.
Apart from defining the new instructions, the main changes are:
- Adding VR128, VR64 and VR32 register classes.
- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.
- Adding a D(V,B) addressing mode for scatter/gather operations
- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields.
Until now all immediate operands have been the same width as the
underlying field (hence the assert->return change in decode[SU]ImmOperand).
In addition, sys::getHostCPUName is extended to detect running natively
on a z13 machine.
Based on a patch by Richard Sandiford.
llvm-svn: 236520
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index ec6a573..0d00359 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -39,13 +39,17 @@
ADDR64Reg,
FP32Reg,
FP64Reg,
- FP128Reg
+ FP128Reg,
+ VR32Reg,
+ VR64Reg,
+ VR128Reg
};
enum MemoryKind {
BDMem,
BDXMem,
- BDLMem
+ BDLMem,
+ BDVMem
};
class SystemZOperand : public MCParsedAsmOperand {
@@ -89,10 +93,10 @@
// the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
// length for D(L,B)-style operands, otherwise it is null.
struct MemOp {
- unsigned Base : 8;
- unsigned Index : 8;
- unsigned MemKind : 8;
- unsigned RegKind : 8;
+ unsigned Base : 12;
+ unsigned Index : 12;
+ unsigned MemKind : 4;
+ unsigned RegKind : 4;
const MCExpr *Disp;
const MCExpr *Length;
};
@@ -246,6 +250,13 @@
bool isMemDisp12Len8(RegisterKind RegKind) const {
return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
}
+ void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 3 && "Invalid number of operands");
+ assert(isMem(BDVMem) && "Invalid operand type");
+ Inst.addOperand(MCOperand::CreateReg(Mem.Base));
+ addExpr(Inst, Mem.Disp);
+ Inst.addOperand(MCOperand::CreateReg(Mem.Index));
+ }
// Override MCParsedAsmOperand.
SMLoc getStartLoc() const override { return StartLoc; }
@@ -307,6 +318,10 @@
bool isFP32() const { return isReg(FP32Reg); }
bool isFP64() const { return isReg(FP64Reg); }
bool isFP128() const { return isReg(FP128Reg); }
+ bool isVR32() const { return isReg(VR32Reg); }
+ bool isVR64() const { return isReg(VR64Reg); }
+ bool isVF128() const { return false; }
+ bool isVR128() const { return isReg(VR128Reg); }
bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
@@ -314,10 +329,15 @@
bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
+ bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
+ bool isU1Imm() const { return isImm(0, 1); }
+ bool isU2Imm() const { return isImm(0, 3); }
+ bool isU3Imm() const { return isImm(0, 7); }
bool isU4Imm() const { return isImm(0, 15); }
bool isU6Imm() const { return isImm(0, 63); }
bool isU8Imm() const { return isImm(0, 255); }
bool isS8Imm() const { return isImm(-128, 127); }
+ bool isU12Imm() const { return isImm(0, 4095); }
bool isU16Imm() const { return isImm(0, 65535); }
bool isS16Imm() const { return isImm(-32768, 32767); }
bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
@@ -334,6 +354,7 @@
enum RegisterGroup {
RegGR,
RegFP,
+ RegV,
RegAccess
};
struct Register {
@@ -352,7 +373,7 @@
RegisterKind Kind);
bool parseAddress(unsigned &Base, const MCExpr *&Disp,
- unsigned &Index, const MCExpr *&Length,
+ unsigned &Index, bool &IsVector, const MCExpr *&Length,
const unsigned *Regs, RegisterKind RegKind);
OperandMatchResultTy parseAddress(OperandVector &Operands,
@@ -419,6 +440,18 @@
OperandMatchResultTy parseFP128(OperandVector &Operands) {
return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
}
+ OperandMatchResultTy parseVR32(OperandVector &Operands) {
+ return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
+ }
+ OperandMatchResultTy parseVR64(OperandVector &Operands) {
+ return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
+ }
+ OperandMatchResultTy parseVF128(OperandVector &Operands) {
+ llvm_unreachable("Shouldn't be used as an operand");
+ }
+ OperandMatchResultTy parseVR128(OperandVector &Operands) {
+ return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
+ }
OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
}
@@ -431,6 +464,9 @@
OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
}
+ OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
+ return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
+ }
OperandMatchResultTy parseAccessReg(OperandVector &Operands);
OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
@@ -484,6 +520,8 @@
Reg.Group = RegGR;
else if (Prefix == 'f' && Reg.Num < 16)
Reg.Group = RegFP;
+ else if (Prefix == 'v' && Reg.Num < 32)
+ Reg.Group = RegV;
else if (Prefix == 'a' && Reg.Num < 16)
Reg.Group = RegAccess;
else
@@ -534,8 +572,8 @@
// Regs maps asm register numbers to LLVM register numbers and RegKind
// says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
- unsigned &Index, const MCExpr *&Length,
- const unsigned *Regs,
+ unsigned &Index, bool &IsVector,
+ const MCExpr *&Length, const unsigned *Regs,
RegisterKind RegKind) {
// Parse the displacement, which must always be present.
if (getParser().parseExpression(Disp))
@@ -544,6 +582,7 @@
// Parse the optional base and index.
Index = 0;
Base = 0;
+ IsVector = false;
Length = nullptr;
if (getLexer().is(AsmToken::LParen)) {
Parser.Lex();
@@ -551,12 +590,23 @@
if (getLexer().is(AsmToken::Percent)) {
// Parse the first register and decide whether it's a base or an index.
Register Reg;
- if (parseRegister(Reg, RegGR, Regs, RegKind))
+ if (parseRegister(Reg))
return true;
- if (getLexer().is(AsmToken::Comma))
- Index = Reg.Num;
- else
- Base = Reg.Num;
+ if (Reg.Group == RegV) {
+ // A vector index register. The base register is optional.
+ IsVector = true;
+ Index = SystemZMC::VR128Regs[Reg.Num];
+ } else if (Reg.Group == RegGR) {
+ if (Reg.Num == 0)
+ return Error(Reg.StartLoc, "%r0 used in an address");
+ // If the are two registers, the first one is the index and the
+ // second is the base.
+ if (getLexer().is(AsmToken::Comma))
+ Index = Regs[Reg.Num];
+ else
+ Base = Regs[Reg.Num];
+ } else
+ return Error(Reg.StartLoc, "invalid address register");
} else {
// Parse the length.
if (getParser().parseExpression(Length))
@@ -587,28 +637,36 @@
const unsigned *Regs, RegisterKind RegKind) {
SMLoc StartLoc = Parser.getTok().getLoc();
unsigned Base, Index;
+ bool IsVector;
const MCExpr *Disp;
const MCExpr *Length;
- if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
+ if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
return MatchOperand_ParseFail;
- if (Index && MemKind != BDXMem)
- {
- Error(StartLoc, "invalid use of indexed addressing");
- return MatchOperand_ParseFail;
- }
+ if (IsVector && MemKind != BDVMem) {
+ Error(StartLoc, "invalid use of vector addressing");
+ return MatchOperand_ParseFail;
+ }
- if (Length && MemKind != BDLMem)
- {
- Error(StartLoc, "invalid use of length addressing");
- return MatchOperand_ParseFail;
- }
+ if (!IsVector && MemKind == BDVMem) {
+ Error(StartLoc, "vector index required in address");
+ return MatchOperand_ParseFail;
+ }
- if (!Length && MemKind == BDLMem)
- {
- Error(StartLoc, "missing length in address");
- return MatchOperand_ParseFail;
- }
+ if (Index && MemKind != BDXMem && MemKind != BDVMem) {
+ Error(StartLoc, "invalid use of indexed addressing");
+ return MatchOperand_ParseFail;
+ }
+
+ if (Length && MemKind != BDLMem) {
+ Error(StartLoc, "invalid use of length addressing");
+ return MatchOperand_ParseFail;
+ }
+
+ if (!Length && MemKind == BDLMem) {
+ Error(StartLoc, "missing length in address");
+ return MatchOperand_ParseFail;
+ }
SMLoc EndLoc =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -631,6 +689,8 @@
RegNo = SystemZMC::GR64Regs[Reg.Num];
else if (Reg.Group == RegFP)
RegNo = SystemZMC::FP64Regs[Reg.Num];
+ else if (Reg.Group == RegV)
+ RegNo = SystemZMC::VR128Regs[Reg.Num];
else
// FIXME: Access registers aren't modelled as LLVM registers yet.
return Error(Reg.StartLoc, "invalid operand for instruction");
@@ -703,8 +763,10 @@
// so we treat any plain expression as an immediate.
SMLoc StartLoc = Parser.getTok().getLoc();
unsigned Base, Index;
+ bool IsVector;
const MCExpr *Expr, *Length;
- if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
+ if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
+ ADDR64Reg))
return true;
SMLoc EndLoc =