commit a94b9e33af7ed2aca9f3466cbe17eb93cb8d586e
author Rafael Espindola <rafael.espindola@gmail.com> Thu Aug 03 17:02:20 2006 +0000
committer Rafael Espindola <rafael.espindola@gmail.com> Thu Aug 03 17:02:20 2006 +0000
tree 46800ff32d5af0414bfa08b7ee2dce92ab127210
parent baf6ef94c134c4d7bb47a5a773c4e73d161e185d

add and use ARMISD::RET_FLAG

llvm-svn: 29499

llvm/lib/Target/ARM/ARMInstrInfo.td

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index a749aa0..5ba4deb 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -44,6 +44,8 @@
 def SDT_ARMcall    : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
 def ARMcall        : SDNode<"ARMISD::CALL", SDT_ARMcall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+def retflag        : SDNode<"ARMISD::RET_FLAG", SDTRet,
+	                   [SDNPHasChain, SDNPOptInFlag]>;
 
 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
@@ -54,7 +56,7 @@
                                [(callseq_start imm:$amt)]>;
 
 let isReturn = 1 in {
-  def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+  def bx: InstARM<(ops), "bx r14", [(retflag)]>;
 }
 
 let  Defs = [R0, R1, R2, R3] in {