AMDGPU: Use correct method for determining instruction size
llvm-svn: 273172
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
index 0a6b5c0..f08106a 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
-; CHECK: {{^}}inline_asm:
+; CHECK-LABEL: {{^}}inline_asm:
; CHECK: s_endpgm
; CHECK: s_endpgm
define void @inline_asm(i32 addrspace(1)* %out) {
@@ -11,7 +11,7 @@
ret void
}
-; CHECK: {{^}}inline_asm_shader:
+; CHECK-LABEL: {{^}}inline_asm_shader:
; CHECK: s_endpgm
; CHECK: s_endpgm
define amdgpu_ps void @inline_asm_shader() {
@@ -38,7 +38,7 @@
ret void
}
-; CHECK: {{^}}v_cmp_asm:
+; CHECK-LABEL: {{^}}v_cmp_asm:
; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]]
; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
@@ -49,3 +49,31 @@
store i64 %sgpr, i64 addrspace(1)* %out
ret void
}
+
+; CHECK-LABEL: {{^}}code_size_inline_asm:
+; CHECK: codeLenInByte = 12
+define void @code_size_inline_asm(i32 addrspace(1)* %out) {
+entry:
+ call void asm sideeffect "v_nop_e64", ""()
+ ret void
+}
+
+; All inlineasm instructions are assumed to be the maximum size
+; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:
+; CHECK: codeLenInByte = 12
+define void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) {
+entry:
+ call void asm sideeffect "v_nop_e32", ""()
+ ret void
+}
+
+; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:
+; CHECK: codeLenInByte = 20
+define void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) {
+entry:
+ call void asm sideeffect "
+ v_nop_e64
+ v_nop_e64
+ ", ""()
+ ret void
+}