commit a9bb00d82b42697464855db1e2e8846bc149bfac
author Jonas Paulsson <paulsson@linux.vnet.ibm.com> Wed Jan 18 08:32:54 2017 +0000
committer Jonas Paulsson <paulsson@linux.vnet.ibm.com> Wed Jan 18 08:32:54 2017 +0000
tree 1cd49a26ed6bafc8178dbffda731fbe1f94a3c46
parent 197db00e3ea7c6c5f2178e22ffb78061153203ff

[SystemZ] Proper handling of undef flag while expanding pseudo.

During post-RA pseudo expansion, an 'undef' flag of the source operand should
be propagated by emitGRX32Move().

Review: Ulrich Weigand
llvm-svn: 292353

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 4019fc4..4c65899 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -131,7 +131,8 @@
     MI.setDesc(get(LowOpcodeK));
   else {
     emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
-                  SystemZ::LR, 32, MI.getOperand(1).isKill());
+                  SystemZ::LR, 32, MI.getOperand(1).isKill(),
+                  MI.getOperand(1).isUndef());
     MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
     MI.getOperand(1).setReg(DestReg);
     MI.tieOperands(0, 1);
@@ -187,7 +188,7 @@
                                         unsigned Size) const {
   emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
                 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
-                Size, MI.getOperand(1).isKill());
+                Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
   MI.eraseFromParent();
 }
 
@@ -231,7 +232,8 @@
                                      MachineBasicBlock::iterator MBBI,
                                      const DebugLoc &DL, unsigned DestReg,
                                      unsigned SrcReg, unsigned LowLowOpcode,
-                                     unsigned Size, bool KillSrc) const {
+                                     unsigned Size, bool KillSrc,
+                                     bool UndefSrc) const {
   unsigned Opcode;
   bool DestIsHigh = isHighReg(DestReg);
   bool SrcIsHigh = isHighReg(SrcReg);
@@ -243,13 +245,13 @@
     Opcode = SystemZ::RISBLH;
   else {
     BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
+      .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
     return;
   }
   unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
     .addReg(DestReg, RegState::Undef)
-    .addReg(SrcReg, getKillRegState(KillSrc))
+    .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
     .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
 }
 
@@ -814,7 +816,8 @@
   }
 
   if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
-    emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
+    emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
+                  false);
     return;
   }