commit a9d68f140e3077645534ac518ef08d2dfa6a70cc
author Chris Lattner <sabre@nondot.org> Fri Aug 19 00:31:37 2005 +0000
committer Chris Lattner <sabre@nondot.org> Fri Aug 19 00:31:37 2005 +0000
tree 6c26d3a99f83af137dda3dbdfe544ca328625650
parent 145695927a019d98f10e65cc2af2e9fb5364e9c0

The variable SAR's only take one operand too

llvm-svn: 22888

llvm/lib/Target/X86/X86ISelPattern.cpp

diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp
index e78a9df..0ebd629 100644
--- a/llvm/lib/Target/X86/X86ISelPattern.cpp
+++ b/llvm/lib/Target/X86/X86ISelPattern.cpp
@@ -3283,7 +3283,7 @@
     case MVT::i32: Opc = X86::SAR32rCL; break;
     }
     BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2);
-    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::SETCC: