[X86] Fix a few instructions that were named Z512 instead of just Z.
This makes things consistent with our normal instruction naming.
llvm-svn: 320316
diff --git a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
index 2890fd6..a46f22f 100644
--- a/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
@@ -583,12 +583,12 @@
case X86::VPSLLDQYri:
case X86::VPSLLDQZ128rr:
case X86::VPSLLDQZ256rr:
- case X86::VPSLLDQZ512rr:
+ case X86::VPSLLDQZrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
LLVM_FALLTHROUGH;
case X86::VPSLLDQZ128rm:
case X86::VPSLLDQZ256rm:
- case X86::VPSLLDQZ512rm:
+ case X86::VPSLLDQZrm:
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
@@ -601,12 +601,12 @@
case X86::VPSRLDQYri:
case X86::VPSRLDQZ128rr:
case X86::VPSRLDQZ256rr:
- case X86::VPSRLDQZ512rr:
+ case X86::VPSRLDQZrr:
Src1Name = getRegName(MI->getOperand(1).getReg());
LLVM_FALLTHROUGH;
case X86::VPSRLDQZ128rm:
case X86::VPSRLDQZ256rm:
- case X86::VPSRLDQZ512rm:
+ case X86::VPSRLDQZrm:
DestName = getRegName(MI->getOperand(0).getReg());
if (MI->getOperand(NumOperands - 1).isImm())
DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),