[PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.
Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning
is the others need all their operands to be sign/zero extended for their output
to also be sign/zero extended. This is true for AND and sign-extension, but for
zero-extension we only need at least one of the input operands to be zero
extended for the result to also be zero extended.
Differential Revision: https://reviews.llvm.org/D39078
llvm-svn: 319289
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index a035ec6..fd56663 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2378,9 +2378,7 @@
}
// If all incoming values are sign-/zero-extended,
- // the output of AND, OR, ISEL or PHI is also sign-/zero-extended.
- case PPC::AND:
- case PPC::AND8:
+ // the output of OR, ISEL or PHI is also sign-/zero-extended.
case PPC::OR:
case PPC::OR8:
case PPC::ISEL:
@@ -2411,6 +2409,36 @@
return true;
}
+ // If at least one of the incoming values of an AND is zero extended
+ // then the output is also zero-extended. If both of the incoming values
+ // are sign-extended then the output is also sign extended.
+ case PPC::AND:
+ case PPC::AND8: {
+ if (Depth >= MAX_DEPTH)
+ return false;
+
+ assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
+
+ unsigned SrcReg1 = MI.getOperand(1).getReg();
+ unsigned SrcReg2 = MI.getOperand(2).getReg();
+
+ if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
+ !TargetRegisterInfo::isVirtualRegister(SrcReg2))
+ return false;
+
+ const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
+ const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
+ if (!MISrc1 || !MISrc2)
+ return false;
+
+ if(SignExt)
+ return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
+ isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ else
+ return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
+ isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
+ }
+
default:
break;
}