[RISCV] Rename FPRs and use Register arithmetic
The new names for FPRs ensure that the Register values within the same class are
enumerated consecutively (the order is determined by the `LessRecordRegister`
function object). Where there were tables mapping between 32- and 64-bit FPRs
(and vice versa) this patch replaces them with Register arithmetic. The
enumeration order between different register classes is expected to continue to
be arbitrary, although it does impact the conversion from the (overloaded) asm
FPR names to Register values, and therefore might require updates to the target
if the sorting algorithm is changed. Static asserts were added to ensure that
changes to the ordering that would impact the current implementation are
detected.
Differential Revision: https://reviews.llvm.org/D67423
llvm-svn: 373096
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.td b/llvm/lib/Target/RISCV/RISCVCallingConv.td
index db13e6e..025454f 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.td
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.td
@@ -18,11 +18,11 @@
def CSR_ILP32F_LP64F
: CalleeSavedRegs<(add CSR_ILP32_LP64,
- F8_32, F9_32, (sequence "F%u_32", 18, 27))>;
+ F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
def CSR_ILP32D_LP64D
: CalleeSavedRegs<(add CSR_ILP32_LP64,
- F8_64, F9_64, (sequence "F%u_64", 18, 27))>;
+ F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
def CSR_NoRegs : CalleeSavedRegs<(add)>;
@@ -43,12 +43,12 @@
(sequence "X%u", 12, 17),
(sequence "X%u", 18, 27),
(sequence "X%u", 28, 31),
- (sequence "F%u_32", 0, 7),
- (sequence "F%u_32", 10, 11),
- (sequence "F%u_32", 12, 17),
- (sequence "F%u_32", 28, 31),
- (sequence "F%u_32", 8, 9),
- (sequence "F%u_32", 18, 27))>;
+ (sequence "F%u_F", 0, 7),
+ (sequence "F%u_F", 10, 11),
+ (sequence "F%u_F", 12, 17),
+ (sequence "F%u_F", 28, 31),
+ (sequence "F%u_F", 8, 9),
+ (sequence "F%u_F", 18, 27))>;
// Same as CSR_Interrupt, but including all 64-bit FP registers.
def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
@@ -57,9 +57,9 @@
(sequence "X%u", 12, 17),
(sequence "X%u", 18, 27),
(sequence "X%u", 28, 31),
- (sequence "F%u_64", 0, 7),
- (sequence "F%u_64", 10, 11),
- (sequence "F%u_64", 12, 17),
- (sequence "F%u_64", 28, 31),
- (sequence "F%u_64", 8, 9),
- (sequence "F%u_64", 18, 27))>;
+ (sequence "F%u_D", 0, 7),
+ (sequence "F%u_D", 10, 11),
+ (sequence "F%u_D", 12, 17),
+ (sequence "F%u_D", 28, 31),
+ (sequence "F%u_D", 8, 9),
+ (sequence "F%u_D", 18, 27))>;