MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
llvm-svn: 32034
diff --git a/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp b/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp
index 55140e3..65bacb8 100644
--- a/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp
+++ b/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp
@@ -53,7 +53,8 @@
// 0. bc opcode
// 1. reg
// 2. target MBB
- MBBI->setOpcode(MBBI->getOperand(0).getImm());
+ const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
+ MBBI->setInstrDescriptor(TII->get(MBBI->getOperand(0).getImm()));
}
}
}