commit ab41193312ff0fd06648c1bad63f02d36578dfb8
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 02 03:50:56 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 02 03:50:56 2018 +0000
tree 2ebc44bdf2f65ad4ebb4c53cf6416c099aaf69a2
parent 6f77811a211e3fdc1d1796b8b32cd38f5c1933ba

AMDGPU: Expand atomicrmw nand in IR

llvm-svn: 343559

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 3b0026a..ae6b925 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -4477,3 +4477,10 @@
     return false;
   }
 }
+
+TargetLowering::AtomicExpansionKind
+AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
+  if (RMW->getOperation() == AtomicRMWInst::Nand)
+    return AtomicExpansionKind::CmpXChg;
+  return AtomicExpansionKind::None;
+}

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index a231265..92d8991 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -307,6 +307,8 @@
   MVT getFenceOperandTy(const DataLayout &DL) const override {
     return MVT::i32;
   }
+
+  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 };
 
 namespace AMDGPUISD {

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index f3fe0ae..f6ebc3d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -602,6 +602,7 @@
   disablePass(&FuncletLayoutID);
   disablePass(&PatchableFunctionID);
 
+  addPass(createAtomicExpandPass());
   addPass(createAMDGPULowerIntrinsicsPass());
 
   if (TM.getTargetTriple().getArch() == Triple::r600 ||