commit ab51cf2e78023c5a9c715bb27d68e0b492822e16
author Evan Cheng <evan.cheng@apple.com> Fri Oct 13 21:14:26 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Oct 13 21:14:26 2006 +0000
tree d33b0d76086cbb54952be211b41c47ffc246e913
parent df1ca3ff63b92c3c7c5d89d0ec43cf724a05236f

Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.

llvm-svn: 30945

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 900dd3c..d2fd3cd 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -47,6 +47,9 @@
   setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
   setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
   
+  // PowerPC does not have truncstore for i1.
+  setStoreXAction(MVT::i1, Promote);
+
   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
 
@@ -117,9 +120,6 @@
   setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
   setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
 
-  // PowerPC does not have truncstore for i1.
-  setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
-
   // We cannot sextinreg(i1).  Expand to shifts.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   
@@ -743,7 +743,9 @@
   // memory location argument.
   MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
-  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), Op.getOperand(2));
+  SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
+  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
+                      SV->getOffset());
 }
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
@@ -898,8 +900,7 @@
       unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
       MF.addLiveIn(GPR[GPR_idx], VReg);
       SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
-      SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN,
-                                     DAG.getSrcValue(NULL));
+      SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
       SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
@@ -1033,8 +1034,7 @@
       if (GPR_idx != NumGPRs) {
         RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
       } else {
-        MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
-                                           DAG.getSrcValue(NULL)));
+        MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
       }
       ArgOffset += PtrByteSize;
       break;
@@ -1044,8 +1044,7 @@
         RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
 
         if (isVarArg) {
-          SDOperand Store = DAG.getStore(Chain, Arg, PtrOff,
-                                         DAG.getSrcValue(NULL));
+          SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
           MemOpChains.push_back(Store);
 
           // Float varargs are always shadowed in available integer registers
@@ -1071,8 +1070,7 @@
             ++GPR_idx;
         }
       } else {
-        MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff,
-                                           DAG.getSrcValue(NULL)));
+        MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
       }
       if (isPPC64)
         ArgOffset += 8;
@@ -2119,7 +2117,7 @@
   
   // Store the input value into Value#0 of the stack slot.
   SDOperand Store = DAG.getStore(DAG.getEntryNode(),
-                                 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
+                                 Op.getOperand(0), FIdx, NULL, 0);
   // Load it out.
   return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
 }