[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
llvm-svn: 342891
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 9e84a67..3e44014 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6841,6 +6841,15 @@
"destination operands must be sequential");
break;
}
+ case ARM::VLDMDIA:
+ case ARM::VSTMDIA: {
+ ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
+ auto &RegList = Op.getRegList();
+ if (RegList.size() < 1 || RegList.size() > 16)
+ return Error(Operands[3]->getStartLoc(),
+ "list of registers must be at least 1 and at most 16");
+ break;
+ }
}
return false;