Remove some register allocation order dependencies.
llvm-svn: 172874
diff --git a/llvm/test/CodeGen/ARM/fabss.ll b/llvm/test/CodeGen/ARM/fabss.ll
index 46c2f1c..c3e00ce 100644
--- a/llvm/test/CodeGen/ARM/fabss.ll
+++ b/llvm/test/CodeGen/ARM/fabss.ll
@@ -14,12 +14,12 @@
declare float @fabsf(float)
; VFP2: test:
-; VFP2: vabs.f32 s2, s2
+; VFP2: vabs.f32 s
; NFP1: test:
-; NFP1: vabs.f32 d1, d1
+; NFP1: vabs.f32 d
; NFP0: test:
-; NFP0: vabs.f32 s2, s2
+; NFP0: vabs.f32 s
; CORTEXA8: test:
; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
diff --git a/llvm/test/CodeGen/ARM/fdivs.ll b/llvm/test/CodeGen/ARM/fdivs.ll
index 8fab002..8f13f39 100644
--- a/llvm/test/CodeGen/ARM/fdivs.ll
+++ b/llvm/test/CodeGen/ARM/fdivs.ll
@@ -10,14 +10,14 @@
}
; VFP2: test:
-; VFP2: vdiv.f32 s0, s2, s0
+; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
; NFP1: test:
-; NFP1: vdiv.f32 s0, s2, s0
+; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
; NFP0: test:
-; NFP0: vdiv.f32 s0, s2, s0
+; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
; CORTEXA8: test:
-; CORTEXA8: vdiv.f32 s0, s2, s0
+; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
; CORTEXA9: test:
; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
diff --git a/llvm/test/CodeGen/ARM/fnmscs.ll b/llvm/test/CodeGen/ARM/fnmscs.ll
index 6081712..9ce9b7a 100644
--- a/llvm/test/CodeGen/ARM/fnmscs.ll
+++ b/llvm/test/CodeGen/ARM/fnmscs.ll
@@ -46,8 +46,8 @@
; NEON: vnmla.f64
; A8: t3:
-; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
-; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
+; A8: vnmul.f64 d
+; A8: vsub.f64 d
%0 = fmul double %a, %b
%1 = fsub double -0.0, %0
%2 = fsub double %1, %acc
@@ -63,8 +63,8 @@
; NEON: vnmla.f64
; A8: t4:
-; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
-; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
+; A8: vnmul.f64 d
+; A8: vsub.f64 d
%0 = fmul double %a, %b
%1 = fmul double -1.0, %0
%2 = fsub double %1, %acc