commit ac79c7c4c077a3b85989e7b620f3ba081bcfa24f
author Evan Cheng <evan.cheng@apple.com> Wed Nov 01 00:27:05 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Nov 01 00:27:05 2006 +0000
tree f150764831c2e243fb032d07e1e6cc3959950e42
parent 7a6a5b9af501e5c71da76e68fa15fc3d594cacdf

Add operand constraints to TargetInstrInfo.

llvm-svn: 31333

llvm/utils/TableGen/DAGISelEmitter.cpp

diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 4f5a731..dfeea10 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -3552,11 +3552,14 @@
   // Emit boilerplate.
   OS << "SDNode *Select_INLINEASM(SDOperand N) {\n"
      << "  std::vector<SDOperand> Ops(N.Val->op_begin(), N.Val->op_end());\n"
-     << "  AddToISelQueue(N.getOperand(0)); // Select the chain.\n\n"
+     << "  AddToISelQueue(N.getOperand(0)); // Select the chain.\n"
      << "  // Select the flag operand.\n"
      << "  if (Ops.back().getValueType() == MVT::Flag)\n"
      << "    AddToISelQueue(Ops.back());\n"
      << "  SelectInlineAsmMemoryOperands(Ops, *CurDAG);\n"
+     << "  for (unsigned i = 2, e = Ops.size(); i < e; ++i)\n"
+     << "    if (Ops[i].getOpcode() != ISD::Constant)\n"
+     << "      AddToISelQueue(Ops[i]);\n"
      << "  std::vector<MVT::ValueType> VTs;\n"
      << "  VTs.push_back(MVT::Other);\n"
      << "  VTs.push_back(MVT::Flag);\n"
@@ -3582,6 +3585,7 @@
      << "  case ISD::TargetConstantPool:\n"
      << "  case ISD::TargetFrameIndex:\n"
      << "  case ISD::TargetJumpTable:\n"
+     << "  case ISD::TargetExternalSymbol:\n"
      << "  case ISD::TargetGlobalAddress: {\n"
      << "    return NULL;\n"
      << "  }\n"