commit ac92e77bb8e585065caf595c590085971b13f0f4
author Owen Anderson <resistor@mac.com> Mon Aug 22 18:22:06 2011 +0000
committer Owen Anderson <resistor@mac.com> Mon Aug 22 18:22:06 2011 +0000
tree 515338384bc933969f301022b9e878318ec2dff9
parent fe29fe431d9463123b2b1e6543629ecb6c57beaa

Correct writeback handling of duplicating VLD instructions.  Discovered by randomized testing.

llvm-svn: 138251

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index ebcb798..725a8a2a 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1992,7 +1992,7 @@
   if (regs == 2) {
     CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
   }
-  if (Rm == 0xD) {
+  if (Rm != 0xF) {
     CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
@@ -2023,7 +2023,7 @@
 
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
-  if (Rm == 0xD) {
+  if (Rm != 0xF) {
     CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
@@ -2052,7 +2052,7 @@
   CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
-  if (Rm == 0xD) {
+  if (Rm != 0xF) {
     CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }
 
@@ -2097,7 +2097,7 @@
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
   CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
-  if (Rm == 0xD) {
+  if (Rm != 0xF) {
     CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   }