ARM VTBL (one register) assembly parsing and encoding.

llvm-svn: 142441
diff --git a/llvm/utils/TableGen/EDEmitter.cpp b/llvm/utils/TableGen/EDEmitter.cpp
index e9edfe4..1a9a9c4 100644
--- a/llvm/utils/TableGen/EDEmitter.cpp
+++ b/llvm/utils/TableGen/EDEmitter.cpp
@@ -571,6 +571,7 @@
   REG("QPR");
   REG("QQPR");
   REG("QQQQPR");
+  REG("VecListOneD");
 
   IMM("i32imm");
   IMM("i32imm_hilo16");