commit adcfe5d88120361aa7d53547279ae4bf9d48f74c
author Yaxun Liu <Yaxun.Liu@amd.com> Tue Aug 15 17:16:44 2017 +0000
committer Yaxun Liu <Yaxun.Liu@amd.com> Tue Aug 15 17:16:44 2017 +0000
tree 518fbfc7fd80512065e3695d0029e3e73410baed
parent 2b6631bb36e3416b3aedba78ea6756b3a760c330

Attempt to fix failure in CodeGenOpenCL/atomic-ops.cl

llvm-svn: 310932

clang/test/CodeGenOpenCL/atomic-ops.cl

diff --git a/clang/test/CodeGenOpenCL/atomic-ops.cl b/clang/test/CodeGenOpenCL/atomic-ops.cl
index da9e0f3..ecc394a 100644
--- a/clang/test/CodeGenOpenCL/atomic-ops.cl
+++ b/clang/test/CodeGenOpenCL/atomic-ops.cl
@@ -1,8 +1,8 @@
-// RUN: %clang_cc1 %s -cl-std=CL2.0 -emit-llvm -O0 -o - -triple=amdgcn-amd-amdhsa-opencl | FileCheck %s
+// RUN: %clang_cc1 %s -cl-std=CL2.0 -emit-llvm -O0 -o - -triple=amdgcn-amd-amdhsa-opencl | opt -instnamer -S | FileCheck %s
 
 // Also test serialization of atomic operations here, to avoid duplicating the test.
 // RUN: %clang_cc1 %s -cl-std=CL2.0 -emit-pch -O0 -o %t -triple=amdgcn-amd-amdhsa-opencl
-// RUN: %clang_cc1 %s -cl-std=CL2.0 -include-pch %t -O0 -triple=amdgcn-amd-amdhsa-opencl -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -cl-std=CL2.0 -include-pch %t -O0 -triple=amdgcn-amd-amdhsa-opencl -emit-llvm -o - | opt -instnamer -S | FileCheck %s
 
 #ifndef ALREADY_INCLUDED
 #define ALREADY_INCLUDED
@@ -87,10 +87,10 @@
   // CHECK: load atomic i32, i32 addrspace(4)* %{{.*}} syncscope("agent") seq_cst
   // CHECK: br label %atomic.scope.continue
   // CHECK: opencl_allsvmdevices:
-  // CHECK: load atomic i32, i32 addrspace(4)* %{{.*}} seq_cst, align 4
+  // CHECK: load atomic i32, i32 addrspace(4)* %{{.*}} seq_cst
   // CHECK: br label %atomic.scope.continue
   // CHECK: opencl_subgroup:
-  // CHECK: %5 = load atomic i32, i32 addrspace(4)* %0 syncscope("subgroup") seq_cst, align 4
+  // CHECK: load atomic i32, i32 addrspace(4)* %{{.*}} syncscope("subgroup") seq_cst
   // CHECK: br label %atomic.scope.continue
   // CHECK: atomic.scope.continue:
   int x = __opencl_atomic_load(i, memory_order_seq_cst, scope);
@@ -116,7 +116,7 @@
   // CHECK-NEXT: i32 4, label %[[ACQ_SUB:.*]]
   // CHECK-NEXT: ]
   // CHECK: seqcst:
-  // CHECK: switch i32 %2, label %[[SEQ_ALL:.*]] [
+  // CHECK: switch i32 %{{.*}}, label %[[SEQ_ALL:.*]] [
   // CHECK-NEXT: i32 1, label %[[SEQ_WG:.*]]
   // CHECK-NEXT: i32 2, label %[[SEQ_DEV:.*]]
   // CHECK-NEXT: i32 4, label %[[SEQ_SUB:.*]]