commit ae719c5a17854f861bb5b74b0a861d402ba5668c
author Simon Dardis <simon.dardis@imgtec.com> Tue Jul 11 18:03:20 2017 +0000
committer Simon Dardis <simon.dardis@imgtec.com> Tue Jul 11 18:03:20 2017 +0000
tree bb1c4124206b3cf25b46de2c67b2750fe0c6a044
parent 94b3b47c73c6c1191c27823a0a5bbb5a020767bf

[mips][mt][1/7] Add the MT ASE as a subtarget feature.

Preparatory work for adding the MIPS MT (multi-threading) ASE instructions.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35247

llvm-svn: 307679

llvm/lib/Target/Mips/MipsSubtarget.cpp

diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 154d582..eba21e0 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -70,7 +70,8 @@
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-      HasEVA(false), DisableMadd4(false), TM(TM), TargetTriple(TT), TSInfo(),
+      HasEVA(false), DisableMadd4(false), HasMT(false), TM(TM),
+      TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),