commit aed6bd6f4293c07ca4c55bf49943943f4425794b
author Sander de Smalen <sander.desmalen@arm.com> Tue May 05 09:16:57 2020 +0100
committer Sander de Smalen <sander.desmalen@arm.com> Tue May 05 10:42:11 2020 +0100
tree f3925d0bc7ca5fdabbcf79864c1c17d119b196b5
parent 40574fefe9b2ad7d251da25c7461c313d965b809

Reland D78750: [SveEmitter] Add builtins for svdupq and svdupq_lane

Edit: Changed a few CHECK lines into CHECK-DAG lines.

This reverts commit 90f3f62cb087782fe2608e95d686c29067281b6e.

clang/utils/TableGen/SveEmitter.cpp

diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp
index 12730d7..d8df92f 100644
--- a/clang/utils/TableGen/SveEmitter.cpp
+++ b/clang/utils/TableGen/SveEmitter.cpp
@@ -94,7 +94,9 @@
   bool isDefault() const { return DefaultType; }
   bool isFloat() const { return Float; }
   bool isInteger() const { return !Float && !Predicate; }
-  bool isScalarPredicate() const { return !Float && ElementBitwidth == 1; }
+  bool isScalarPredicate() const {
+    return !Float && Predicate && NumVectors == 0;
+  }
   bool isPredicateVector() const { return Predicate; }
   bool isPredicatePattern() const { return PredicatePattern; }
   bool isPrefetchOp() const { return PrefetchOp; }
@@ -407,12 +409,12 @@
 
     if (Float)
       S += "float";
-    else if (isScalarPredicate())
+    else if (isScalarPredicate() || isPredicateVector())
       S += "bool";
     else
       S += "int";
 
-    if (!isScalarPredicate())
+    if (!isScalarPredicate() && !isPredicateVector())
       S += utostr(ElementBitwidth);
     if (!isScalableVector() && isVector())
       S += "x" + utostr(getNumElements());
@@ -433,7 +435,6 @@
     switch (I) {
     case 'P':
       Predicate = true;
-      ElementBitwidth = 1;
       break;
     case 'U':
       Signed = false;