commit aff10602072d77d974280f98fb6020c5ed70d4b0
author Jakob Stoklund Olesen <stoklund@2pi.dk> Thu Jun 02 05:43:46 2011 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Thu Jun 02 05:43:46 2011 +0000
tree 80a120acb0fdbb41fc0ef51758eea9a5330f60e6
parent 7f25c32d5b7b232dbce76d0b57817bc335a54ab1

Use TRI::has{Sub,Super}ClassEq() where possible.

No functional change.

llvm-svn: 132455

llvm/lib/CodeGen/TargetInstrInfoImpl.cpp

diff --git a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
index b9fcd38..34e2b33 100644
--- a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -212,8 +212,7 @@
   if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
     return RC->contains(LiveOp.getReg()) ? RC : 0;
 
-  const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg);
-  if (RC == LiveRC || RC->hasSubClass(LiveRC))
+  if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
     return RC;
 
   // FIXME: Allow folding when register classes are memory compatible.