[RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot of the
RISC-V tests.
Differential Revision: https://reviews.llvm.org/D39849
llvm-svn: 320357
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index ba093bb..d92bb70 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -24,7 +24,8 @@
explicit RISCVFrameLowering(const RISCVSubtarget &STI)
: TargetFrameLowering(StackGrowsDown,
/*StackAlignment=*/16,
- /*LocalAreaOffset=*/0) {}
+ /*LocalAreaOffset=*/0),
+ STI(STI) {}
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
@@ -32,6 +33,9 @@
int getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const override;
+ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
+ RegScavenger *RS) const override;
+
bool hasFP(const MachineFunction &MF) const override;
MachineBasicBlock::iterator
@@ -39,6 +43,15 @@
MachineBasicBlock::iterator MI) const override {
return MBB.erase(MI);
}
+
+protected:
+ const RISCVSubtarget &STI;
+
+private:
+ void determineFrameLayout(MachineFunction &MF) const;
+ void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
+ int64_t Val, MachineInstr::MIFlag Flag) const;
};
}
#endif