AMDGPU: Fix incorrect reordering when inline asm defines LDS address
Defs of operands outside of the instruction's explicit defs need
to be checked.
llvm-svn: 324554
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 26ba06a..6f7ae78 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -174,9 +174,10 @@
}
static void addDefsToList(const MachineInstr &MI, DenseSet<unsigned> &Defs) {
- // XXX: Should this be looking for implicit defs?
- for (const MachineOperand &Def : MI.defs())
- Defs.insert(Def.getReg());
+ for (const MachineOperand &Def : MI.operands()) {
+ if (Def.isReg() && Def.isDef())
+ Defs.insert(Def.getReg());
+ }
}
static bool memAccessesCanBeReordered(MachineBasicBlock::iterator A,