commit b0b741efb8478f039d2e018375aa0163c98d42e5
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 30 01:33:14 2018 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Oct 30 01:33:14 2018 +0000
tree 002eb6418d7dcfa8f6fec27edd2b1e3829587822
parent e2f073463e9522b3a7effe1481eeb10a24e8c649

AMDGPU: Use scavengeRegisterBackwards

llvm-svn: 345559

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index aa79ad8..d0d8576 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1555,8 +1555,9 @@
   //   buzz;
 
   RS->enterBasicBlockEnd(MBB);
-  unsigned Scav = RS->scavengeRegister(&AMDGPU::SReg_64RegClass,
-                                       MachineBasicBlock::iterator(GetPC), 0);
+  unsigned Scav = RS->scavengeRegisterBackwards(
+    AMDGPU::SReg_64RegClass,
+    MachineBasicBlock::iterator(GetPC), false, 0);
   MRI.replaceRegWith(PCReg, Scav);
   MRI.clearVirtRegs();
   RS->setRegUsed(Scav);