commit b15000736c4f8a16f7db67b65e9ae20e25bc13e7
author Evan Cheng <evan.cheng@apple.com> Thu Nov 09 17:55:04 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu Nov 09 17:55:04 2006 +0000
tree d0690717f14f7bf1aad7949840a407cb7666ac6e
parent f1606b80f11f4a8dafabd618921e3568f092a2df

Rename ISD::MemOpAddrMode to ISD::MemIndexedMode

llvm-svn: 31595

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d211077..8bbcd26 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -202,7 +202,7 @@
           Ptr.Val->use_size() > 1) {
         SDOperand BasePtr;
         SDOperand Offset;
-        ISD::MemOpAddrMode AM = ISD::UNINDEXED;
+        ISD::MemIndexedMode AM = ISD::UNINDEXED;
         if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
           // Try turning it into a pre-indexed load / store except when
           // 1) Another use of base ptr is a predecessor of N. If ptr is folded
@@ -298,7 +298,7 @@
 
           SDOperand BasePtr;
           SDOperand Offset;
-          ISD::MemOpAddrMode AM = ISD::UNINDEXED;
+          ISD::MemIndexedMode AM = ISD::UNINDEXED;
           if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
             if (Ptr == Offset)
               std::swap(BasePtr, Offset);

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f2e9ea8..3b51679 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1619,8 +1619,9 @@
   return SDOperand(N, 0);
 }
 
-SDOperand SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
-                                       SDOperand Offset, ISD::MemOpAddrMode AM){
+SDOperand
+SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
+                             SDOperand Offset, ISD::MemIndexedMode AM) {
   LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
   assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
          "Load is already a indexed load!");
@@ -1722,8 +1723,9 @@
   return SDOperand(N, 0);
 }
 
-SDOperand SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base,
-                                       SDOperand Offset, ISD::MemOpAddrMode AM){
+SDOperand
+SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base,
+                              SDOperand Offset, ISD::MemIndexedMode AM) {
   StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
   assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
          "Store is already a indexed store!");
@@ -2841,7 +2843,7 @@
   }
 }
 
-const char *SDNode::getAddressingModeName(ISD::MemOpAddrMode AM) {
+const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
   switch (AM) {
   default:
     return "";
@@ -2943,7 +2945,7 @@
     if (doExt)
       std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
 
-    const char *AM = getAddressingModeName(LD->getAddressingMode());
+    const char *AM = getIndexedModeName(LD->getAddressingMode());
     if (AM != "")
       std::cerr << " " << AM;
   } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
@@ -2951,7 +2953,7 @@
       std::cerr << " <trunc "
                 << MVT::getValueTypeString(ST->getStoredVT()) << ">";
 
-    const char *AM = getAddressingModeName(ST->getAddressingMode());
+    const char *AM = getIndexedModeName(ST->getAddressingMode());
     if (AM != "")
       std::cerr << " " << AM;
   }