commit b22f6c5f26730bc8d73904d0c98c71ebc50e2919
author Sanjay Patel <spatel@rotateright.com> Fri Jan 13 18:39:09 2017 +0000
committer Sanjay Patel <spatel@rotateright.com> Fri Jan 13 18:39:09 2017 +0000
tree a98bf46637d771fd883f2a3c8230f11626e29fd5
parent d066f3af61c92710374822c1c91e820ab739a1ee

[InstCombine] use m_APInt to allow shl folds for vectors with splat constants

llvm-svn: 291934

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 7249ef4..a79a630 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -723,8 +723,9 @@
   if (Instruction *V = commonShiftTransforms(I))
     return V;
 
-  if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
-    unsigned ShAmt = Op1C->getZExtValue();
+  const APInt *ShAmtAPInt;
+  if (match(Op1, m_APInt(ShAmtAPInt))) {
+    unsigned ShAmt = ShAmtAPInt->getZExtValue();
 
     // Turn:
     //  %zext = zext i32 %V to i64
@@ -748,7 +749,8 @@
     // If the shifted-out value is known-zero, then this is a NUW shift.
     if (!I.hasNoUnsignedWrap() &&
         MaskedValueIsZero(
-            Op0, APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt), 0, &I)) {
+            Op0, APInt::getHighBitsSet(ShAmtAPInt->getBitWidth(), ShAmt), 0,
+            &I)) {
       I.setHasNoUnsignedWrap();
       return &I;
     }

llvm/test/Transforms/InstCombine/shift.ll

diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 884b541..5f59ab8 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -455,7 +455,7 @@
 define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
 ; CHECK-LABEL: @test25_vector(
 ; CHECK-NEXT:    [[TMP_3:%.*]] = lshr <2 x i32> %tmp.2, <i32 17, i32 17>
-; CHECK-NEXT:    [[TMP_51:%.*]] = shl <2 x i32> [[TMP_3]], <i32 17, i32 17>
+; CHECK-NEXT:    [[TMP_51:%.*]] = shl nuw <2 x i32> [[TMP_3]], <i32 17, i32 17>
 ; CHECK-NEXT:    [[X2:%.*]] = add <2 x i32> [[TMP_51]], %AA
 ; CHECK-NEXT:    [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP_6]]
@@ -671,7 +671,7 @@
 define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
 ; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i8> %x to <2 x i32>
-; CHECK-NEXT:    [[T3:%.*]] = shl <2 x i32> [[T2]], <i32 17, i32 17>
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17>
 ; CHECK-NEXT:    ret <2 x i32> [[T3]]
 ;
   %t2 = zext <2 x i8> %x to <2 x i32>
@@ -1070,8 +1070,8 @@
 define <2 x i64> @test_64_splat_vec(<2 x i32> %t) {
 ; CHECK-LABEL: @test_64_splat_vec(
 ; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> %t, <i32 16777215, i32 16777215>
-; CHECK-NEXT:    [[EXT:%.*]] = zext <2 x i32> [[AND]] to <2 x i64>
-; CHECK-NEXT:    [[SHL:%.*]] = shl <2 x i64> [[EXT]], <i64 8, i64 8>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl nuw <2 x i32> [[AND]], <i32 8, i32 8>
+; CHECK-NEXT:    [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[SHL]]
 ;
   %and = and <2 x i32> %t, <i32 16777215, i32 16777215>