commit b35efba4d9c14dce4642f3b78ac02fd2440c75ce
author Tom Stellard <thomas.stellard@amd.com> Mon May 20 15:02:01 2013 +0000
committer Tom Stellard <thomas.stellard@amd.com> Mon May 20 15:02:01 2013 +0000
tree 0fd76643a398ea7a7d46ef4b2495dce9540db7b8
parent f41e3f56a5b337ac78816c7555add946eed725ca

R600/SI: Make fitsRegClass() operands const

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282

llvm/lib/Target/R600/SIISelLowering.cpp

diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp
index 237999f..a077a95 100644
--- a/llvm/lib/Target/R600/SIISelLowering.cpp
+++ b/llvm/lib/Target/R600/SIISelLowering.cpp
@@ -513,7 +513,7 @@
 }
 
 /// \brief Does "Op" fit into register class "RegClass" ?
-bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
+bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
                                     unsigned RegClass) const {
 
   MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();

llvm/lib/Target/R600/SIISelLowering.h

diff --git a/llvm/lib/Target/R600/SIISelLowering.h b/llvm/lib/Target/R600/SIISelLowering.h
index af0625f..62dfeda 100644
--- a/llvm/lib/Target/R600/SIISelLowering.h
+++ b/llvm/lib/Target/R600/SIISelLowering.h
@@ -30,7 +30,8 @@
 
   bool foldImm(SDValue &Operand, int32_t &Immediate,
                bool &ScalarSlotUsed) const;
-  bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
+  bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
+                    unsigned RegClass) const;
   void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
                        unsigned RegClass, bool &ScalarSlotUsed) const;