commit b370bf329a3a23de0404c1c04175494b2e1a3289
author Devang Patel <dpatel@apple.com> Wed Jan 26 21:41:22 2011 +0000
committer Devang Patel <dpatel@apple.com> Wed Jan 26 21:41:22 2011 +0000
tree d86540d118108a9df63edae69401d84cd702e985
parent 9636753d39c8f9aec4fdb86b014c9a703a98245a

Revert 124301.

llvm-svn: 124327

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 2d7178b..4c9158a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -539,12 +539,8 @@
                     SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
                            SmallSet<unsigned, 8> &Seen) {
   unsigned Order = DAG->GetOrdering(N);
-  if (!Order || !Seen.insert(Order)) {
-    // Process any valid SDDbgValues even if node does not have any order
-    // assigned.
-    ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
+  if (!Order || !Seen.insert(Order))
     return;
-  }
 
   MachineBasicBlock *BB = Emitter.getBlock();
   if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {